PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet
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PI7C9X20404SL PCI EXPRESS PACKET SWITCH DATASHEET REVISION 1.2 July 2009 ST 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) FAX: 408-435-1100 Internet: http://www.pericom.com ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
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... PRSNT) Updated Chapter 4.1 PIN List of 128-PIN LQFP (PRSNT) Modified 5.1 Physical Layer Circuit Updated Chapter 6.1.3 EEPROM Space Address Map (10h to 16h, 50h to 56h) July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine Family ...
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... SMBCLK, SMBDATA, PWR_SAV, CTCDIS, EEPD) Updated Chapter 3.4 JTAG Boundary Scan Signals (TMS, TDI, TRST_L) Updated Chapter 7.2.52 and 7.2.53 Switch Operation Mode (Bit[31:16]) Updated Chapter 13 Ordering Information July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM ...
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... PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................34 7.2.5 REVISION ID REGISTER – OFFSET 08h .........................................................................................34 7.2.6 CLASS CODE REGISTER – OFFSET 08h .........................................................................................34 7.2.7 CACHE LINE REGISTER – OFFSET 0Ch.........................................................................................35 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine Family Datasheet ...
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... NEXT ITEM POINTER REGISTER – OFFSET C0h ..........................................................................47 7.2.58 SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h ....................................................................47 7.2.59 SUBSYSTEM ID REGISTER – OFFSET C4h.....................................................................................48 7.2.60 GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)...............................................48 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine Family Datasheet ...
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... IEEE 1149.1 COMPATIBLE JTAG CONTROLLER....................................................................................69 9.1 INSTRUCTION REGISTER ......................................................................................................................69 9.2 BYPASS REGISTER .................................................................................................................................69 9.3 DEVICE ID REGISTER.............................................................................................................................69 9.4 BOUNDARY SCAN REGISTER...............................................................................................................70 9.5 JTAG BOUNDARY SCAN REGISTER ORDER......................................................................................70 10 POWER MANAGEMENT ................................................................................................................................72 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine Family Datasheet ...
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... ELECTRICAL AND TIMING SPECIFICATIONS .......................................................................................73 11.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................73 11.2 POWER CONSUMPTION.........................................................................................................................73 11.3 DC SPECIFICATIONS ..............................................................................................................................73 11.4 AC SPECIFICATIONS ..............................................................................................................................74 12 PACKAGE INFORMATION............................................................................................................................76 13 ORDERING INFORMATION..........................................................................................................................77 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine Family Datasheet ...
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... ABLE BSOLUTE MAXIMUM RATINGS T 11-2 PI7C9X404SL ABLE POWER DISSIPATION T 11-3 DC ABLE ELECTRICAL CHARACTERISTICS T 11 ABLE RANSMITTER HARACTERISTICS T 11 ABLE ECEIVER HARACTERISTICS July 2009 – Revision 1.2 Pericom Semiconductor I PI7C9X20404SL ............................................................30 MPLEMENTATION ON ................................................................................................................. )............................................................................................16 ALUES NOM N C .............................................................................16 OMINAL URRENT DEQ [3:0]................................................................................................... ..........................................................................................20 RDERING ULES ....................................................................................................30 .....................................................................................................................65 ITS ...
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... Programmable driver current and de-emphasis level at each individual port Low Power Dissipation at 360 mW typical in L0 normal mode, 210 mW typical in L1 standby mode Industrial Temperature Range -40 128-pin LQFP 14mm x 14mm package July 2009 – Revision 1.2 Pericom Semiconductor and L3 link power states Ready and D3 device power states ...
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... The protocol requires that each ingress port maintains the credits independently without checking other ports' credit availability, which is otherwise required by pure output queue architecture. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL ...
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... EEPD 41 SMBCLK 13 SMBDATA 16 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION I Reference Clock Input Pairs: Connect to external 100MHz differential clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered ...
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... TMS 63 TDO 58 TDI 64 TRST_L 65 July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION I/O Full-Scan Enable Control: For normal operation, SCAN_EN is an output with a value of “0”. SCAN_EN becomes an input during manufacturing testing. O Port PHY Error Status: These pins are used to display the PHY Error status of the ports ...
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... July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION P VDDC Supply (1.0V): Used as digital core power pins. P VDDR Supply (3.3V): Used as digital I/O power pins. ...
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... VSS 20 VDDR 21 GPIO[0] 22 GPIO[1] 23 GPIO[2] 24 GPIO[3] 25 GPIO[4] 26 GPIO[5] 27 GPIO[6] 28 GPIO[7] 29 VDDC 30 VSS 31 TEST1 32 P1_CTCDIS July 2009 – Revision 1.2 Pericom Semiconductor PIN NAME PIN 33 P2_CTCDIS 65 34 VSS 66 35 VDDR 67 36 VSS 68 37 VDDC 69 38 P3_CTCDIS 70 39 VDDR 71 40 EECLK 72 41 EEPD ...
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... Table 5-2 Ratio of Actual Current and Nominal Current DTX [3:0] ACTUAL CURRENT / NOMINAL CURRENT 0000 0001 0010 0011 0100 0101 0110 1 Multiple lanes could share the PLL. July 2009 – Revision 1.2 Pericom Semiconductor NOMINAL DRIVER CURENT Reserved 1.00 1.05 1.10 1 ...
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... ISI related jitter. The following table shows a simple guideline for selecting the appropriate value to adapt with different lengths or connector numbers in various applications. Table 5-4 Rx Equalizer Settings (RXEQCTL) RXEQCTL [1] RXEQCTL [ July 2009 – Revision 1.2 Pericom Semiconductor 1.35 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 –I ...
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... If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI protocol. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL ...
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... CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to have payload coming with the header, the payload data would be put into CPLD queue. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page ...
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... Each port has port arbitration circuitries for traffic handling in VC0. At upstream port, in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the arbitration loop to get the service in Virtual Channel 0. July 2009 – Revision 1.2 Pericom Semiconductor Read Non-posted Write Request ...
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... TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e. configuration register) is accessed and regenerate the message that terminated at receiver acts as an upstream port. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL ...
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... EEPROM SPACE ADDRESS MAP 15 – 8 EEPROM Signature (1516h) Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm Reserved July 2009 – Revision 1.2 Pericom Semiconductor 7 – 0 Vendor ID Device ID Subsystem Vender ID Subsystem ID Difference ...
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... Acknowledge Latency Timer for Port 0 Acknowledge Latency Timer for Port 1 Acknowledge Latency Timer for Port 2 Acknowledge Latency Timer for Port 3 July 2009 – Revision 1.2 Pericom Semiconductor 7 – 0 Reserved Slot Clock / LPVC Count / Port Num, Port 0 Slot Implemented / Slot Clock / LPVC Count ...
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... B0h(port 0~3) B0h : Bit [15] B4h(port 0~3) B4h : Bit [15] B0h(port 0~3) B0h : Bit [13] B4h(Port 0~3) B4h: Bit [7] July 2009 – Revision 1.2 Pericom Semiconductor 7 – 0 PHY Parameter for Port 2 PHY Parameter for Port 3 Reserved Reserved Reserved Reserved PM Control Para/Rx Polarity for Port 0 ...
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... A8h(Port 3) A8h: Bit [14:13] B8h (port3) B8h : Bit[11:10] B8h : Bit[12] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch DESCRIPTION TX SOF Latency Mode for Port 0~3 Bit [11]: Set to zero to shorten latency Surprise Down Capability Enable for for Port 0~3 ...
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... ECh: Bit [25:24] 84h (Port 2) 84h: Bit [14:13] 154h (Port 2) 154h: Bit [7:1] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch DESCRIPTION Slot Clock Configuration for Port 0 Bit [1]: When set, the component uses the clock provided on the ...
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... Bit [26] 80h: Bit [29:28] 53h 84h (Port 1) 84h: Bit [31:24] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch DESCRIPTION PCIe Capability Slot Implemented for Port 3 Bit [0]: When set, the slot is implemented for Port 3 Slot Clock Configuration for Port 3 ...
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... B0h – Bit [31:16] 90h B4h (Port 0) B4h: Bit [31:16] 92h B4h (Port 1) B4h: Bit [31:16] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch DESCRIPTION No_Soft_Reset for Port 2 Bit [0]: No_Soft_Reset Power Management Capability for Port 2 ...
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... A6h B0h (Port3) B0h: Bit[31] B4h (Port 3) B4h: Bit [13:8] B4h (Port 3) B4h : Bit [14] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch DESCRIPTION PHY Parameter for Port 2 Bit [31:16]: PHY Parameter PHY Parameter for Port 3 ...
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... Table 6-1 SMBus Address Pin Configuration BIT SMBus Address 0 GPIO[5] 1 GPIO[6] 2 GPIO[ July 2009 – Revision 1.2 Pericom Semiconductor Processor (SMBus Master) SMBCLK Page PI7C9X20404SL 4Port-4Lane PCI Express® Switch TM SlimLine Family Datasheet Other SMBus Devices ...
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... Reserved VPD Register Length in Bytes (14h) ACK Latency Timer PHY Parameters Reserved SSID July 2009 – Revision 1.2 Pericom Semiconductor DEFINITION Hardware Initialization Read Only Read / Write Read / Write 1 to Clear Sticky - Read Only / Write 1 to Clear Sticky - Read / Write Sticky – Read Only 23 – ...
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... Next Capability Offset=20Ch VC Arbitration Table Offset=3 Port VC Status Register Port Arbitration Table Offset=4 VC Resource Status Register (0) Next Capability Offset=000h July 2009 – Revision 1.2 Pericom Semiconductor 23 – Reserved GPIO Data and Control EEPROM Address Next Item Pointer=00 Device Capabilities Device Control ...
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... Wait Cycle Control 8 SERR# enable Fast Back-to-Back 9 Enable 10 Interrupt Disable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION RO Identifies Pericom as the vendor of this device. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 12D8h. TYPE ...
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... BIT FUNCTION 15:8 Programming Interface 23:16 Sub-Class Code 31:24 Base Class Code July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION RO Reset to 0b. TYPE DESCRIPTION RO Reset to 000b. Indicates that an INTx Interrupt Message is pending internally to the device. ...
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... FUNCTION Subordinate Bus 23:16 Number July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION The cache line size register is set by the system firmware and the operating system cache line size. This field is implemented by PCI Express devices as a ...
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... Error 26:25 DEVSEL_L timing Signaled Target 27 Abort Received Target 28 Abort July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. RO TYPE DESCRIPTION RO Read as 01h to indicate 32-bit I/O addressing. Defines the bottom address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other ...
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... PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h BIT FUNCTION 19:16 64-bit addressing July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status in secondary side. ...
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... BIT FUNCTION 7:0 Capability Pointer July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Defines the top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other ...
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... ISA Enable 19 VGA Enable 20 VGA 16-bit decode 21 Master Abort Mode 22 Secondary Bus Reset July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Reset to 80h. TYPE DESCRIPTION RW Reset to 00h. TYPE DESCRIPTION The Switch implements INTA virtual wire interrupt signals to represent hot- plug events at downstream ports ...
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... POWER MANAGEMENT DATA REGISTER – OFFSET 84h BIT FUNCTION 1:0 Power State July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Does not apply to PCI Express. Must be hardwired to 0b. RO Does not apply to PCI Express. Must be hardwired to 0b. ...
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... Data Register 7.2.35 MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) BIT FUNCTION Enhanced 7:0 Capabilities ID July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION 00b: D0 state 01b: D1 state 10b: D2 state 11b: D3 hot state Reset to 00b. ...
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... MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) BIT FUNCTION 15:0 Message Data 7.2.41 VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only) July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Pointer points to the Vendor specific capability register (A4h). RO Reset to A4h. TYPE ...
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... VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h BIT FUNCTION Enhanced 7:0 Capabilities ID July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Read as 03h to indicate that these are VPD enhanced capability registers. RO Reset to 03h. TYPE DESCRIPTION Pointer points to the Vendor specific capability register (A4h) ...
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... Capability Disable MSI Capability 14 Disable AER Capability 15 Disable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Pointer points to the SSID/SSVID capability register (C0h). RO Reset to C0h. TYPE DESCRIPTION The length field provides the information for number of bytes in the capability structure (including the ID and Next pointer bytes) ...
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... Mode Ordering on 6 Different Tag of Completion Mode 7 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION A 14-bit register contains a user-defined value. The default value may be changed by SMBus or auto-loading from EEPROM. RW Reset to 0. When asserted, the user-defined ACK latency value is be employed. The default value may be changed by SMBus or auto-loading from EEPROM ...
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... Inversion Disable Compliance Pattern 15 Parity Control Disable 16 Low Driver Current July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION The default value may be changed by SMBus or auto-loading from EEPROM. RW Reset to 000001b. The default value may be changed by SMBus or auto-loading from EEPROM ...
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... Next Item Pointer 7.2.58 SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h BIT FUNCTION July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION It indicates the status of the strapping pin HIDRV. The default value may be changed by SMBus or auto-loading from EEPROM. ...
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... Enable GPIO [3] Output 14 Register 15 Reserved 16 GPIO [4] Input July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch RO It indicates the sub-system vendor id. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 0000h. TYPE DESCRIPTION RO It indicates the sub-system device id. The default value may be changed by SMBus or auto-loading from EEPROM ...
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... EEPROM Command EEPROM Error 2 Status EEPROM Autoload 3 Success July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION 0b: GPIO [ input pin 1b: GPIO [ output pin RW Reset to 0b. Value of this bit will be output to GPIO [4] pin if GPIO [4] is configured as an output pin. ...
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... PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h BIT FUNCTION 19:16 Capability Version July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION 0b: EEPROM autoload was unsuccessful or is disabled 1b: EEPROM autoload occurred successfully after PREST. Configuration RO registers were loaded with values stored in the EEPROM Reset to 0b ...
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... Limit Value Captured Slot Power 27:26 Limit Scale 31:28 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Indicates the type of PCI Express logical device. RO Reset to 0101b (Upstream port). Reset to 0110b (Downstream port). When set, indicates that the PCIe Link associated with this Port is connected to a slot ...
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... Reserved 7.2.69 DEVICE STATUS REGISTER – OFFSET E8h BIT FUNCTION Correctable Error 16 Detected July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION 0b: Disable Correctable Error Reporting 1b: Enable Correctable Error Reporting RW Reset to 0b. 0b: Disable Non-Fatal Error Reporting ...
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... Latency 18 Reserved Surprise Down Error 19 Reporting Capable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Asserted when non-fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control RW1C register ...
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... LINK STATUS REGISTER – OFFSET F0h BIT FUNCTION 19:16 Link Speed July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION For a Downstream Port, this bit must be set the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine ...
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... Power Indicator 4 Present 5 Hot-Plug Surprise 6 Hot-Plug Capable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Indicates the negotiated width of the given PCIe link. RO Reset to 000001b (x1). When set, indicates a Link training error occurred. This bit is cleared by hardware upon successful training of the link to the L0 RO link state ...
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... Enable Attention Indicator 7:6 Control July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION It applies to Downstream Port only. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Writes to this register also cause the Port to send the Set_Slot_Power_Limit message. The RW default value may be changed by SMBus or auto-loading from EEPROM ...
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... Presence Detect State 23 Reserved Data Link Layer 24 State Changed 31:25 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Controls the display of Power Indicator. 00b: Reserved 01b: On 10b: Blink RW 11b: Off Writes to this register also cause the Port to send the POWER_INDICATOR_* Messages ...
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... Completion Status Receiver Overflow 17 Status Malformed TLP 18 Status July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Read as 0001h to indicate that these are PCI express extended capability RO registers for advance error reporting. TYPE DESCRIPTION Read as 1h. Indicates PCI-SIG defined PCI Express capability structure version number ...
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... ECRC Error Mask Unsupported Request 20 Error Mask 31:21 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION When set, indicates that an ECRC Error has been detected. RW1CS Reset to 0b. When set, indicates that an Unsupported Request event has occurred. ...
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... CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h BIT FUNCTION 0 Receiver Error Status 5:1 Reserved 6 Bad TLP Status July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION 0b: Non-Fatal 1b: Fatal RWS Reset to 1b. RO Reset to 000b. 0b: Non-Fatal 1b: Fatal RWS Reset to 1b ...
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... FUNCTION 4:0 First Error Pointer ECRC Generation 5 Capable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION When set, the event of Bad DLLP has been received is detected. RW1CS Reset to 0b. When set, the REPLAY_NUM Rollover event is detected. ...
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... BIT FUNCTION 2:0 Extended VC Count 3 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION When set, it enables the generation of ECRC when needed. RWS Reset to 0b. When set, it indicates the Switch has the capability to check ECRC. ...
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... FUNCTION VC Arbitration Table 16 Status 31:17 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION It indicates the number of extended Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group. The default value may RO be changed by SMBus or auto-loading from EEPROM. ...
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... VC ID 30:27 Reserved 31 VC Enable July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION It indicates the types of Port Arbitration supported by the VC resource. The Switch supports Hardware fixed arbitration scheme, e.g., Round Robin, Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports) RO and Time-based WRR with 128 phases (3~4 enabled ports) ...
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... Capabilities ID 7.2.98 CAPABILITY VERSION – OFFSET 20Ch BIT FUNCTION July 2009 – Revision 1.2 Pericom Semiconductor TYPE DESCRIPTION RO Reset to 0000h. When set, it indicates that any entry of the Port Arbitration Table is written by software. This bit is cleared when hardware finishes loading values stored in RO the Port Arbitration Table after the bit of “ ...
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... PM Sub State 14:13 PM State 17:15 Type 20:18 Power Rail 31:21 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION Read as 1h. Indicates PCIe Base Specification compliance. RO Reset to 1h. TYPE DESCRIPTION Read as 000h. No other ECP registers. ...
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... FUNCTION 0 System Allocated 31:1 Reserved July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch TYPE DESCRIPTION When set, it indicates that the power budget for the device is included within the system power budget. The default value may be changed by auto-loading RO from EEPROM ...
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... Duty cycle of input clock Rise/Fall time of input clock Differential input voltage swing SW a. RCUI (Reference Clock Unit Interval) refers to the reference clock period July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Min Typical Max. - 100 (peak-to-peak) 800 ...
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... Type 31-28 RO 27- July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Register Selected Operation Boundary Scan Drives / receives off-chip test data Boundary Scan Samples inputs / pre-loads outputs Bypass Tri-states output and I/O pins except TDO pin ...
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... GPIO[ GPIO[ GPIO[ GPIO[ TEST1 28 HIDRV 29 LOWDRV 30 DTX[3] 31 EECLK 32 EEPD 33 34 PERST_L 35 PWR_IND[1] 36 PWR_IND[3] 37 PORTERR[0] 38 ATT_IND[1] 39 ATT_IND[3] July 2009 – Revision 1.2 Pericom Semiconductor Pin Page PI7C9X20404SL 4Port-4Lane PCI Express® Switch TM SlimLine Family Datasheet Type Tri-state Control Cell Input ...
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... DWNRST_L[1] 53 DWNRST_L[2] 54 DWNRST_L[3] 55 PWR_IND[2] 56 TEST6 57 ATT_IND[2] 58 ATT_RTN[2] 59 SLOTCLK 60 PRSNT[2] 61 PWR_ENA[2] 62 PWR_FLT[2] 63 SLOT_IMP[1] July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Pin No Type 47 Output2 Input Input 51 Output2 Input Input Output2 Output2 Input Input 54 Output2 66 Input 96 Output2 97 Output2 98 Output2 ...
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... PI7C9X20404SL forwards power management messages to the upstream Switches or root complex. PI7C9X20404SL also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X20404SL supports beacon generation and WAKEUP_L signal. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM ...
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... VDDAUX: digital auxiliary power supply for the core VTT: transmit termination power supply for PCI Express Interface In order to support auxiliary power management fully recommended to have VDDC and VDDAUX separated. July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Typical Power Dissipation (mW) 360 510 ...
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... Minimum swing assumes LoDrv = 1, HiDrv = 0 and Dtx =1100 c. Max swing assumes LoDrv = 0, HiDrv = 1, Dtx = 0010, VTT = 1. measured between 20% and 80% points. Will depend on package characteristics. e. Measured using PCI Express Compliance Pattern July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Min Typical 400 ...
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... Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Min Typical 170 ...
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... PACKAGE INFORMATION The package of PI7C9X20404SL is a 14mm x 14mm LQFP (128 Pin) package. The following are the package information and mechanical dimension: Figure 12-1 Package outline drawing July 2009 – Revision 1.2 Pericom Semiconductor 4Port-4Lane PCI Express® Switch Page PI7C9X20404SL TM SlimLine ...
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... ORDERING INFORMATION Part Number □ PI7C9X20404SL FDEX PI 7C 9X20404SL July 2009 – Revision 1.2 Pericom Semiconductor Temperature Range Package 128-pin LQFP (Industrial Temperature) 14mm x 14mm Blank=Tray X=Tape & Reel Blank=Standard E=Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number ...