PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 13

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

3.4 JTAG BOUNDARY SCAN SIGNALS
July 2009 – Revision 1.2
Pericom Semiconductor
NAME
SCAN_EN
PORTERR [3:0]
GPIO [7:0]
PWR_SAV
P0_CTCDIS
P1_CTCDIS
P2_CTCDIS
P3_CTCDIS
TEST1/3/4/5/6
TEST2
NAME
TMS
TDO
TDI
TRST_L
TCK
56
54, 51, 47, 45
28, 27, 26, 25,
24, 23, 22, 21
17
18
32
33
38
31, 12, 11, 10,
126
66
59
63
58
64
65
PIN
PIN
TYPE
TYPE
I/O
I/O
O
O
I
I
I
I
I
I
I
Page 13 of 77
DESCRIPTION
Full-Scan Enable Control: For normal operation, SCAN_EN is an
output with a value of “0”. SCAN_EN becomes an input during
manufacturing testing.
Port PHY Error Status: These pins are used to display the PHY Error
status of the ports. When PORTERR is flashing (alternating high and
low signals), it indicates that a PHY error is detected. When it is low,
no PHY error is detected. PORTERR [x] is correspondent to Port x,
where x=0,1,2,3.
General Purpose Input and Output: These eight general-purpose
pins are programmed as either input-only or bi-directional pins by
writing the GPIO output enable control register.
When SMBus is implemented, GPIO[7:5] act as the SMBus address
pins, which set Bit 2 to 0 of the SMBus address.
Power Saving Mode: PWR_SAV is a strapping pin. When this pin is
pulled high when system is reset, the Power Saving Mode is enabled.
When this pin is pulled low when system is reset, the Power Saving
Mode is disabled. When this pin is pulled low, it should be tied to
ground through a pull-down resistor. When this pin is pulled high, a
pull-up resistor should be used. The suggested value for the pull-up and
pull-down resistor is 5.1K. Pin has an internal pull-down.
P0/P1/P2/P3 CTC Disable: These pins should be tied to ground
through a pull-down resistor. The suggested value for the pull-down
resistor is 5.1K. The pins have internal pull-down.
Test1/3/4/5/6: These pins are for internal test purpose. Test1/3/4/5/6
should be tied to ground through a pull-down resistor. The suggested
value for the pull-down resistor is 5.1K.
Test2: This pin is for internal test purpose. Test2 should be tied to
3.3V through a pull-up resistor. The suggested value for the pull-up
resistor is 5.1K.
DESCRIPTION
Test Clock: Used to clock state information and data into and out of
the chip during boundary scan. When JTAG boundary scan function is
not implemented, this pin should be left open (NC).
Test Mode Select: Used to control the state of the Test Access Port
controller. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be pulled low through a
5.1K pull-down resistor.
Test Data Output: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data out of the Test Access Port (TAP) in a serial bit
stream. When JTAG boundary scan function is not implemented, this
pin should be left open (NC).
Test Data Input: When SCAN_EN is high, it is used (in conjunction
with TCK) to shift data and instructions into the TAP in a serial bit
stream. The pin has internal pull-up. When JTAG boundary scan
function is not implemented, this pin should be left open (NC).
Test Reset (Active LOW): Active LOW signal to reset the TAP
controller into an initialized state. The pin has internal pull-up. When
JTAG boundary scan function is not implemented, this pin should be
pulled low through a 5.1K pull-down resistor.
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
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