PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 65

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.95
7.2.96
7.2.97
7.2.98
July 2009 – Revision 1.2
Pericom Semiconductor
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h (Upstream Only)
PORT ARBITRATION TABLE REGISTER (0) – OFFSET 180h-1BCh
(Upstream Only)
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-1 Table Entry Size in 4 Bits
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
CAPABILITY VERSION – OFFSET 20Ch
BIT
15:0
16
17
31:18
BIT
15:0
BIT
[111:110]
[127:126]
[15:14]
[31:30]
[47:46]
[63:62]
[79:78]
[95:94]
63 - 56
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
FUNCTION
Reserved
Port Arbitration
Table Status
VC Negotiation
Pending
Reserved
FUNCTION
Extended
Capabilities ID
FUNCTION
[109:108]
[125:124]
[13:12]
[29:28]
[45:44]
[61:60]
[77:76]
[93:92]
55 - 48
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[107:106]
[123:122]
47 - 40
[11:10]
[27:26]
[43:42]
[59:58]
[75:74]
[91:90]
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
[105:104]
[121:120]
[25:24]
[41:40]
[57:56]
[73:72]
[89:88]
39 - 32
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[9:8]
Page 65 of 77
DESCRIPTION
Reset to 0000h.
When set, it indicates that any entry of the Port Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the Port Arbitration Table after the bit of “Load Port Arbitration Table” is set.
Reset to 0b.
When set, it indicates that the VC resource is still in the process of
negotiation. This bit is cleared after the VC negotiation is complete.
Reset to 0b.
Reset to 0.
DESCRIPTION
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
DESCRIPTION
[103:102]
[119:118]
[23:22]
[39:38]
[55:54]
[71:70]
[87:86]
31 - 24
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[7:6]
[101:100]
[117:116]
23 - 16
[21:20]
[37:36]
[53:52]
[69:68]
[85:84]
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[5:4]
4Port-4Lane PCI Express® Switch
[115:114]
[19:18]
[35:34]
[51:50]
[67:66]
[83:82]
[99:98]
15 - 8
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[3:2]
[113:112]
[17:16]
[33:32]
[49:48]
[65:64]
[81:80]
[97:96]
Phase
Phase
Phase
Phase
Phase
Phase
Phase
Phase
[1:0]
7 - 0
SlimLine
PI7C9X20404SL
Byte Location
Datasheet
TM
00h
08h
10h
18h
20h
28h
30h
38h
Family