PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 40

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.29
7.2.30
7.2.31
7.2.32
July 2009 – Revision 1.2
Pericom Semiconductor
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
NEXT ITEM POINTER REGISTER – OFFSET 80h
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
23
24
25
26
27
31:28
BIT
7:0
BIT
15:8
BIT
18:16
19
20
21
24:22
25
26
31:27
BIT
1:0
FUNCTION
Fast Back-to-Back
Enable
Primary Master
Timeout
Secondary Master
Timeout
Master Timeout
Status
Discard Timer
SERR# enable
Reserved
FUNCTION
Enhanced
Capabilities ID
FUNCTION
Next Item Pointer
FUNCTION
Power Management
Revision
PME# Clock
Reserved
Device Specific
Initialization
AUX Current
D1 Power State
Support
D2 Power State
Support
PME# Support
FUNCTION
Power State
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 40 of 77
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0h.
DESCRIPTION
Read as 01h to indicate that these are power management enhanced capability
registers.
DESCRIPTION
At upstream ports, the pointer points to the Vital Protocol Data (VPD)
capability register (9Ch).
At downstream ports, the pointer points to the Message capability register
(8Ch).
Reset to 9Ch (Upstream port).
Reset to 8Ch (Downstream port).
DESCRIPTION
Read as 011b to indicate the device is compliant to Revision 1.2 of PCI
Power Management Interface Specifications.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Read as 0b to indicate Switch does not have device specific initialization
requirements. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default
value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Switch supports the D1 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 1b to indicate Switch supports the D2 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
Read as 11111b to indicate Switch supports the forwarding of PME# message
in all power states. The default value may be changed by SMBus or auto-
loading from EEPROM.
DESCRIPTION
Indicates the current power state of the Switch. Writing a value of D0 when
the previous state was D3 cause a hot reset without asserting DWNRST_L.
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
TM
Family