PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 20

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

5.7
Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including
Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer
model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering
requirement among transactions within different TC labels.
1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and
message request must complete on the egress bus of VPPB in the order in which they are received on the ingress
bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted
Requests occurring before it.
2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push
the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read
Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data.
Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data.
3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ‘‘pull’’ ahead of previously queued
posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the
posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted
transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If
the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory
Write or Message Request.
4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction.
Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship.
5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as
Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions
are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write
queue and the Non-posted transaction queue.
5.8 PORT ARBITRATION
Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be
forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted
Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC
channel. Each port has port arbitration circuitries for traffic handling in VC0. At upstream port, in addition to the
traffic from inter-port, the intra-port packet such as configurations completion would also join the arbitration loop to
get the service in Virtual Channel 0.
July 2009 – Revision 1.2
Pericom Semiconductor
Table 5-4 Summary of PCI Express Ordering Rules
Row Pass Column
Posted Request
Read Request
Non-posted Write Request
Read Completion
Non-Posted Write
Completion
TRANSACTION ORDERING
Posted
Request
Yes/No
No
No
Yes/No
Yes
2
2
4
1
3
Request
Yes
Yes
Yes
Yes
Yes
Read
5
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Non-posted Write
Request
Yes
Yes
Yes
Yes
Yes
5
Read
Completion
Yes
Yes
Yes
Yes
Yes
4Port-4Lane PCI Express® Switch
5
Non-posted Write
Completion
Yes
Yes
Yes
Yes
Yes
5
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