PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 12

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

3
3.1 PCI EXPRESS INTERFACE SIGNALS
3.2 PORT CONFIGURATION SIGNALS
3.3 MISCELLANEOUS SIGNALS
July 2009 – Revision 1.2
Pericom Semiconductor
PIN DESCRIPTION
NAME
REFCLKP
REFCLKN
PERP [3:0]
PERN [3:0]
PETP [3:0]
PETN [3:0]
WAKEUP_L
PERST_L
DWNRST_L [3:1]
NAME
PRSNT [3:1]
SLOTCLK
NAME
EECLK
EEPD
SMBCLK
SMBDATA
9, 7, 128
127
91
93
120, 104, 87,
70
121, 103, 88,
69
117, 107, 84,
73
116, 108, 83,
74
6
43
98, 97, 96
40
41
13
16
PIN
PIN
PIN
TYPE
TYPE
TYPE
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
Page 12 of 77
DESCRIPTION
Present: When asserted low, it represents the device is present in the
slot of downstream ports. Otherwise, it represents the absence of the
device. PRSNT [x] is correspondent to Port x, where x=1,2,3. The pins
have internal pull-down.
Slot Clock Configuration: It determines if the downstream component
uses the same physical reference clock that the platform provides on
the connector. By default, all downstream ports use the same physical
reference clock provided by platform. The pin has internal pull-down.
DESCRIPTION
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PCI Express Data Serial Input Pairs: Differential data receive
signals in four ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
Port 3 (Downstream Port) is PERP[3] and PERN[3]
PCI Express Data Serial Output Pairs: Differential data transmit
signals in four ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
Port 3 (Downstream Port) is PETP[3] and PETN[3]
Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the
upstream port has to generate a Beacon that is propagated to the Root
Complex/Power Management Controller. Pin has an internal pull-up.
System Reset (Active LOW): When PERST_L is asserted, the
internal states of whole chip except sticky logics are initialized.
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either PERST_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2,3.
DESCRIPTION
EEPROM Clock: Clock signal to the EEPROM interface.
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin is set to 1 by default. The pin has internal pull-up.
SMBus Clock: System management Bus Clock. The pin has internal
pull-up.
SMBus Data: Bi-directional System Management Bus Data. The pin
has internal pull-up.
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
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