PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 27

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PI7C9X20404SLCFDE

Manufacturer Part Number
PI7C9X20404SLCFDE
Description
IC PCIE PACKET SWITCH 128LQFP
Manufacturer
Pericom Semiconductor
Series
SlimLine™r

Specifications of PI7C9X20404SLCFDE

Applications
Data Transport
Interface
Advanced Configuration Power Interface (ACPI)
Package / Case
128-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-

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July 2009 – Revision 1.2
Pericom Semiconductor
ADDRESS
26h
32h
34h
36h
42h
44h
46h
50h
51h
52h
53h
PCI CFG OFFSET
E0h (Port 3)
E0h: Bit [24]
F0h (Port 3)
F0h: Bit [28]
80h (Port 3)
80h: Bit[21]
ECh (Port 3)
ECh: Bit [25:24]
84h (Port 3)
84h: Bit [14:13]
154h (Port 3)
154h: Bit [7:1]
F4h (Port 1)
F4h: Bit [15:0]
F4h (Port 2)
F4h: Bit [15:0]
F4h (Port 3)
F4h: Bit [15:0]
F4h (Port 1)
F4h: Bit [31:16]
F4h (Port 2)
F4h: Bit [31:16]
F4h (Port 3)
F4h: Bit [31:16]
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
84h (Port 0)
84h: Bit [31:24]
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
84h (Port 1)
84h: Bit [31:24]
DESCRIPTION
PCIe Capability Slot Implemented for Port 3
Slot Clock Configuration for Port 3
Device specific Initialization for Port 3
Port Number for Port 3
PMCSR Data Scale for Port 3
Bit [7:6]: It represents the PMCSR Data Scale for physical port 3
VC0 TC/VC Map for Port 3
Slot Capability 0 of Port 1
Slot Capability 0 of Port 2
Slot Capability 0 of Port 3
Slot Capability 1 of Port 1
Slot Capability 1 of Port 2
Slot Capability 1 of Port 3
No_Soft_Reset for Port 0
Power Management Capability for Port 0
Power Management Data for Port 0
No_Soft_Reset for Port 1
Power Management Capability for Port 1
Power Management Data for Port 1
Page 27 of 77
Bit [0]: When set, the slot is implemented for Port 3
Bit [1]: When set, the component uses the clock provided on the
Bit [2]: When set, the DSI is required
Bit [5:4]: It represents the logic port numbering for physical port
3
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the high word of slot capability register
Bit [15:0]: Mapping to the high word of slot capability register
Bit [15:0]: Mapping to the high word of slot capability register
Bit [0]: No_Soft_Reset.
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8]: read only as Data register
Bit [0]: No_Soft_Reset.
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8]: read only as Data register
Connector
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
TM
Family

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