PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 37

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.17
7.2.18
7.2.19
7.2.20
July 2009 – Revision 1.2
Pericom Semiconductor
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
BIT
29
30
31
BIT
3:0
15:4
BIT
19:16
31:20
BIT
3:0
15:4
BIT
19:16
FUNCTION
Received Master
Abort
Received System
Error
Detected Parity Error
FUNCTION
Reserved
Memory Base
Address [15:4]
FUNCTION
Reserved
Memory Limit
Address [31:20]
FUNCTION
64-bit addressing
Prefetchable Memory
Base Address [31:20]
FUNCTION
64-bit addressing
TYPE
TYPE
TYPE
TYPE
TYPE
RWC
RWC
RW
RW
RW
RO
RO
RO
RO
RO
Page 37 of 77
DESCRIPTION
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status in secondary side.
Reset to 0b.
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Bridge Control register is 1.
Reset to 0b.
Set to 1 whenever the secondary side of the port in a Switch receives a
Poisoned TLP.
Reset to 0b.
DESCRIPTION
Reset to 0h.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory transactions from one interface to the other. The
upper 12 bits correspond to address bits [31:20] and are able to be written to.
The lower 20 bits corresponding to address bits [19:0] are assumed to be 0.
Reset to 000h.
DESCRIPTION
Reset to 0h.
Defines the top address of an address range for the Bridge to determine when
to forward memory transactions from one interface to the other. The upper
12 bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
Reset to 000h.
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
Defines the bottom address of an address range for the Bridge to determine
when to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be 0. The memory base register upper 32
bits contain the upper half of the base address.
Reset to 000h.
DESCRIPTION
Read as 0001b to indicate 64-bit addressing.
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
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