PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 54

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.71
7.2.72
July 2009 – Revision 1.2
Pericom Semiconductor
LINK CONTROL REGISTER – OFFSET F0h
LINK STATUS REGISTER – OFFSET F0h
BIT
20
23:21
31:24
BIT
1:0
2
3
4
5
6
7
15:8
BIT
19:16
FUNCTION
Data Link Layer
Active Reporting
Capable
Reserved
Port Number
FUNCTION
Active State Power
Management
(ASPM) Control
Reserved
Read Completion
Boundary (RCB)
Link Disable
Retrain Link
Common Clock
Configuration
Extended Synch
Reserved
FUNCTION
Link Speed
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
R0
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DESCRIPTION
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug capable Downstream
Port, this bit must be set to 1b.
For Upstream Port, this bit must be hardwired to 0b.
Reset to 0b for upstream port.
Reset to 1b for downstream ports.
Reset to 000b
Indicates the PCIe Port Number for the given PCIe Link. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h for Port 0.
Reset to 01h for Port 1.
Reset to 02h for Port 2.
Reset to 03h for Port 3.
DESCRIPTION
00b: ASPM is Disabled
01b: L0s Entry Enabled
10b: L1 Entry Enabled
11b: L0s and L1 Entry Enabled
Note that the receiver must be capable of entering L0s even when the field is
disabled.
Reset to 00b.
Reset to 0b.
Does not apply to PCI Express Switch. Returns ‘0’ when read.
Reset to 0b.
At upstream port, it is not allowed to disable the link, so this bit is hardwired
to ‘0’. For downstream ports, it disables the link when this bit is set.
Reset to 0b.
At upstream port, it is not allowed to retrain the link, so this bit is hardwired
to 0b. For downstream ports, it initiates Link Retraining when this bit is set.
This bit always returns 0b when read.
0b: The components at both ends of a link are operating with asynchronous
1b: The components at both ends of a link are operating with a distributed
Reset to 0b.
When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0
state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state.
Reset to 0b.
Reset to 00h.
DESCRIPTION
Read as 0001b to indicate the negotiated speed of the Express link is 2.5
Gb/s.
reference clock
common reference clock
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
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Family