PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 33

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.1
7.2.2
7.2.3
July 2009 – Revision 1.2
Pericom Semiconductor
VENDOR ID REGISTER – OFFSET 00h
DEVICE ID REGISTER – OFFSET 00h
COMMAND REGISTER – OFFSET 04h
BIT
15:0
BIT
31:16
BIT
0
1
2
3
4
5
6
7
8
9
10
FUNCTION
Vendor ID
FUNCTION
Device ID
FUNCTION
I/O Space Enable
Memory Space
Enable
Bus Master Enable
Special Cycle Enable
Memory Write And
Invalidate Enable
VGA Palette Snoop
Enable
Parity Error
Response Enable
Wait Cycle Control
SERR# enable
Fast Back-to-Back
Enable
Interrupt Disable
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
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Identifies Pericom as the vendor of this device. The default value may be
DESCRIPTION
changed by SMBus or auto-loading from EEPROM.
Reset to 12D8h.
DESCRIPTION
Identifies this device as the PI7C9X20404SL. The default value may be
changed by SMBus or auto-loading from EEPROM.
Resets to A404h.
DESCRIPTION
0b: Ignores I/O transactions on the primary interface
1b: Enables responses to I/O transactions on the primary interface
Resets to 0b.
0b: Ignores memory transactions on the primary interface
1b: Enables responses to memory transactions on the primary interface
Reset to 0b.
0b: Does not initiate memory or I/O transactions on the upstream port and
1b: Enables the Switch Port to forward memory and I/O Read/Write
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
0b: Switch may ignore any parity errors that it detects and continue normal
1b: Switch must take its normal action when a parity error is detected
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0.
0b: Disables the reporting of Non-fatal and Fatal errors detected by the
b1: Enables the Non-fatal and Fatal error reporting to Root Complex
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the ability of a PCI Express device to generate INTx Interrupt
Messages. In the Switch, this bit does not affect the forwarding of INTx
messages from the downstream ports.
Reset to 0b.
operation
handles as an Unsupported Request (UR) to memory and I/O transactions
on the downstream port. For Non-Posted Requests, a completion with UR
completion status must be returned
transactions in the upstream direction
Switch to the Root Complex
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
TM
Family