PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 18

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

5.2
The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK
protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is
protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the
incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK
data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be
sent out to acknowledge on reception of a good TLP.
In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK
DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller
than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is
returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is
triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted
after that packet.
Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit.
All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded
by 16-bit CRC to detect if data corruption occurs.
In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew,
scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is
implemented to interface physical layer with data link layer.
5.3
The receiving end of the transaction layer performs header information retrieval and TC/VC mapping (see section
5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain illegal header
or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an
error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the
TLP at the receiver if the digest bit is set in header.
5.4
The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing.
For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are
routed by their destination ID constituted of bus number, device number, and function number. Address routing is
employed to forward I/O or memory transactions to the destination port, which is located within the address range
indicated by the address field carried in the packet header. The packet header indicates the packet types including
memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message.
Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power
management, and so on. The message type embedded in the packet header determines the routing mechanism.
If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or
targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI
protocol.
July 2009 – Revision 1.2
Pericom Semiconductor
DATA LINK LAYER (DLL)
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION)
ROUTING
Page 18 of 77
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
TM
Family