PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 4

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7/10/08
9/5/08
10/3/08
11/24/08
7/20/09
July 2009 – Revision 1.2
Pericom Semiconductor
0.8
0.9
1.0
1.1
1.2
Modified 1. Features
Updated Chapter 1 Features (updated Industrial Temperature Range)
Updated Chapter 1 Features (power dissipation)
Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers
(0Ch: Ordering Frozen, TX SOF Latency, Surprise Down Capability Enable,
Power Management Data Select, 20h, 22h, 24h: Removed LPVC, Added
PMCSR, 51h, 52h, 53h, 54h, 55h, 56h)
Updated Chapter 7.2 Transparent Mode Configuration Registers (A4h, B4h,
B8, BCh, C0h, C4h)
Updated 7.2.5 Revision ID Register, 7.2.27 Interrupt Pin Register, 7.2.32
Power Management Data Register Bit[3], 7.2.46 Next Item Pointer Register,
7.2.50 Replay Time-Out Counter, 7.2.51 Acknowledge Latency Timer,
7.5.52 Switch Operation Mode, 7.2.53 Switch Operation Mode
(Downstream Port) Bit[16:31], 7.2.54 XPIP CSR2, 7.2.55 SSID/SSVID
Capability ID Register, 7.2.56 Next Item Pointer Register, 7.2.57 Subsystem
Vendor ID Register, 7.2.58 Subsystem ID Register, 7.2.65 PCI Express
Capabilities Register Bit[19:16], 7.2.69 Link Capabilities Register Bit 19,
7.2.86 Capability Version Bit[19:16], 7.2.93 VC Resource Control Register
Bit [26:24], 7.2.97 Capability Version Bit[19:16]
Modified 3.3 Miscellaneous Signals (DEQ[3] to P0_CTCDIS, HIDRV to
P1_CTCDIS, LODRV to P2_CTCDIS, DTX[3] to P3_CTCDIS)
Modified 4.1 Pin List (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS,
LODRV to P2_CTCDIS, DTX[3] to P3_CTCDIS)
Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers
(0Ch, 10h, 12h, 14h, 16h)
Corrected 7.2.27 Interrupt Pin Register
Added 7.2.55 TL CSR
Modified 11.2 Power Consumption
Updated Section 11.1 Absolute Maximum Ratings: Ambient Temperature
with power applied
Updated Figure 12-1 Package outline drawing
Modified 11.2 Power Consumption
Corrected Chapter 7.2 (8Ch - Next Item Pointer)
Updated Figure 12-1 Package outline drawing
Updated Chapter 13 Ordering Information
Removed “Preliminary” and “Confidential” references
Updated Chapter 3.2 Port Configuration Signals (PRSNT, SLOTCLK)
Updated Chapter 3.3 Miscellaneous Signals (updated PWR_SAV pin,
SMBCLK, SMBDATA, PWR_SAV, CTCDIS, EEPD)
Updated Chapter 3.4 JTAG Boundary Scan Signals (TMS, TDI, TRST_L)
Updated Chapter 7.2.52 and 7.2.53 Switch Operation Mode (Bit[31:16])
Updated Chapter 13 Ordering Information
Page 4 of 77
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