PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 39

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.26
7.2.27
7.2.28
July 2009 – Revision 1.2
Pericom Semiconductor
INTERRUPT LINE REGISTER – OFFSET 3Ch
INTERRUPT PIN REGISTER – OFFSET 3Ch
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
BIT
7:0
BIT
15:8
BIT
16
17
18
19
20
21
22
FUNCTION
FUNCTION
Interrupt Line
FUNCTION
Interrupt Pin
FUNCTION
Parity Error
Response
S_SERR# enable
ISA Enable
VGA Enable
VGA 16-bit decode
Master Abort Mode
Secondary Bus Reset
TYPE
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RO
RO
Page 39 of 77
DESCRIPTION
Reset to 80h.
DESCRIPTION
Reset to 00h.
DESCRIPTION
The Switch implements INTA virtual wire interrupt signals to represent hot-
plug events at downstream ports. The default value on the downstream ports
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
DESCRIPTION
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
Reset to 0b.
0b: Forwards downstream all I/O addresses in the address range defined by
1b: Forwards upstream all I/O addresses in the address range defined by the
Reset to 0b.
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
Does not apply to PCI Express. Must be hardwired to 0b.
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
Reset to 0b.
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
ERR_FATAL from secondary to primary interface
ERR_FATAL from secondary to primary interface
the I/O Base, I/O Base, and Limit registers
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
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