PI7C9X20404SLCFDE Pericom Semiconductor, PI7C9X20404SLCFDE Datasheet - Page 53

• Manufacturer Part Number: PI7C9X20404SLCFDE
• Description: IC PCIE PACKET SWITCH 128LQFP
• Manufacturer: Pericom Semiconductor
• Series: SlimLine™r

Specifications of PI7C9X20404SLCFDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.70
July 2009 – Revision 1.2
Pericom Semiconductor
LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
17
18
19
20
21
31:22
BIT
3:0
11:10
14:12
17:15
18
19
9:4
FUNCTION
Non-Fatal Error
Detected
Fatal Error Detected
Unsupported Request
Detected
AUX Power
Detected
Transactions Pending
Reserved
FUNCTION
Maximum Link
Speed
Maximum Link
Width
Active State Power
Management
(ASPM) Support
L0s Exit Latency
L1 Exit
Latency
Reserved
Surprise Down Error
Reporting Capable
RW1C
RW1C
RW1C
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 53 of 77
DESCRIPTION
Asserted when non-fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Reset to 0b.
Asserted when fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Reset to 0b.
Asserted when unsupported request is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register.
Reset to 0b.
Asserted when the AUX power is detected by the Switch
Reset to 1b.
Each port of Switch does not issue Non-posted Requests on its own behalf, so
this bit is hardwired to 0b.
Reset to 0b.
Reset to 0.
DESCRIPTION
Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s.
Indicates the maximum width of the given PCIe Link. The width of each port
is determined by strapped pin or EEPROM pre-loaded value.
Reset to 000001b (x1) for Port 0.
Reset to 000001b (x1) for Port 1.
Reset to 000001b (x1) for Port 2.
Reset to 000001b (x1) for Port 3.
Indicates the level of ASPM supported on the given PCIe Link. Each port of
Switch supports L0s and L1 entry. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 01b.
Indicates the L0s exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be changed
by SMBus or auto-loading from EEPROM.
Reset to 011b.
Indicates the L1 exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L1 to L0 is in
the range of 16us to less than 32us. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 0b.
For a Downstream port, this bit must be set to 1b if the component supports
the optional capability of detecting and reporting a Surprise Down error
condition.
For Upstream Ports, which does not support this optional capability, this bit
must be hardwired to 0b.
Rest to 0b.
4Port-4Lane PCI Express® Switch
SlimLine
PI7C9X20404SL
Datasheet
TM
Family