MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 117

• Manufacturer Part Number: MC68HC711K4CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711K4CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 24KB
• Total Internal Ram Size: 768Byte
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

5.5 Interrupts
M68HC11K Family
MOTOROLA
The MCU has 18 interrupt vectors that support 22 interrupt sources. The
19 maskable interrupts are generated by on-chip peripheral systems.
They are recognized when the I bit in the CCR is clear. The three
non-maskable interrupt sources are illegal opcode trap, software
interrupt, and XIRQ pin.
assignments for each source.
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– The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related
Serial peripheral interface (SPI)
– The SPI system is disabled by reset.
– The port pins associated with this function default to being
Analog-to-digital (A/D) converter
– The ADPU bit in the OPTION register is cleared, disabling the
– The conversion complete flag in the ADCTL register is also
System
– The external IRQ pin has the highest I-bit interrupt priority
– The RBOOT, SMOD, and MDA bits in the HPRIO register
– The IRQ pin is configured for level-sensitive operation for
– The DLY control bit in the OPTION register is set, enabling
– The clock monitor system is disabled because the CME and
status bits are cleared.
general-purpose I/O lines.
A/D system.
cleared.
because PSEL[4:0] in the HPRIO register are initialized with
the value %00110 (where % indicates a binary value).
reflect the status of the MODB and MODA inputs at the rising
edge of reset.
wired-OR systems.
oscillator startup delay after recovery from stop mode.
FCME bits in the OPTION register are cleared.
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Resets and Interrupts
Table 5-5
lists the interrupt sources and vector
Resets and Interrupts
Technical Data
Interrupts
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