PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 185

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
12NC 9397 750 14321
Product data sheet
Bit
6
5:3
2:1
0
Offset 0x04,712C
31:7
6
5:3
2:1
0
Offset 0x04,7200
31:7
6
Symbol
turn_off_ack
sel_clk_dvdd_src
sel_clk_dvdd
en_clk_dvdd
Reserved
turn_off_ack
sel_clk_dtl_mmio_src
sel_clk_dtl_mmio
en_dtl_mmio
Reserved
turn_off_ack
CLK_DTL_MMIO_CTL
CLK_QVCP_OUT_CTL
Acces
s
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
…Continued
Value
0
111
00
1
-
0
000
00
1
-
0
Rev. 2 — 1 December 2004
Description
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_dvdd_src = clk_144
001: clk_dvdd_src = clk_123
010: clk_dvdd_src = clk_108
011: clk_dvdd_src = clk_96
100: clk_dvdd_src = clk_86
101: clk_dvdd_src = clk_78
110: clk_dvdd_src = clk_72
111: clk_dvdd_src = clk_54
00: clk_dvdd = 27 MHz xtal_clk
01: clk_dvdd = clk_dvdd_src
10: clk_dvdd = 27 MHz xtal_clk
11: clk_dvdd = AO_SD[2]
1: enable clk_dvdd
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_dtl_mmio_src = clk_102
001: clk_dtl_mmio_src = clk_108
010: clk_dtl_mmio_src = clk_115
011: clk_dtl_mmio_src = clk_123
100: clk_dtl_mmio_src = clk_133
101: clk_dtl_mmio_src = clk_144
110: clk_dtl_mmio_src = clk_157
111: clk_dtl_mmio_src = clk_54
00: clk_dtl_mmio = 27 MHz xtal_clk
01: clk_dtl_mmio = clk_dtl_mmio_src
10: clk_dtl_mmio = 27 MHz xtal_clk
11: clk_dtl_mmio = AO_SD[3]
1: enable clk_dtl_mmio
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 5: The Clock Module
PNX15xx Series
5-41