PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 423

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 1: VIP Submodule Descriptions
12NC 9397 750 14321
Product data sheet
Submodule
Pre-Dither and Post-
Dither
Up Sample
Horizontal Poly
Phase FIR
Down Sample
AUX Data Extract
3 Channel Write
DMA Control
Figure 2:
VIP Module Interface
2.2.1 Data Routing and Video Modes
Brief Description of Functionality
Video input pipe AUX windower. This submodule:
receives aux samples from Video Port Input module.
captures desired samples in a programmable captured window and/or within a buffer space.
captures ANC packet with matching DID
captures all valid input samples
forwards the captured samples to Pixel Packer.
• There are two identical Dither units: Pre-Dither and Post-Dither, capable of 10->9, 10->8 and 9->8
• 4:2:2 to 4:4:4 Interpolation FIR Filter for chroma upsampling
• Horizontal scaler pipeline
• 4:4:4 to 4:2:2 Decimation FIR Filter for chroma down sampling
• An interface to the memory agent
2.2 Chip I/O and Connections
dithering/rounding of the video data only. The recommended mode is to have rounding for 10->9
and dithering for 9->8
8-bit video samples are received from Post-Dither.
Figure 2
Chip
the PNX15xx Series I/O pins.
The VIP can be operated in three different modes.
SD Video Mode
The interleaved data (YUV) is captured from the dv_data[9:0] input, also called
Channel A. The dv_d_data, also called Channel B, is not used in the SD mode.
HD Mode
The Y data is expected on dv_d_data[9:0] (Channel B) and U/V data is expected on
dv_data[9:0] (Channel A).
RAW MODE
In RAW mode the data can be captured from Channel A or B.
Resources,
sketches the input pins of the VIP module. Refer to
…Continued
Section 7. on page 3-16
Rev. 2 — 1 December 2004
dv_d_data[9:0] (Channel B)
hrefhd
vrefhd
frefhd
dv_data[9:0] (Channel A)
VIP
for the mapping of the VIP I/O signal with
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 3 System On
12-3