PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 659

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 10: VLD Registers
12NC 9397 750 14321
Product data sheet
Bit
2
1
0
Offset 0x07 5014
31:16
15:8
7:0
Offset 0x07 518
31:17
16
15:8
7:3
2
1
0
Offset 0x07 501C
31:0
Offset 0x07 5020
31:15
14:0
Offset 0x07 5024
31:0
Symbol
Bitstream error
Start code detected
VLD Command done
Reserved
Reserved
VLD Int. Enables
Reserved
slice_start_code_strobe
slice_start_code
Reserved
DMA-input-done-mode
Reserved
Little_Endian
VLD Input Memory
Address
Reserved
VLD Input Count
MB Header Memory
Address
…Continued
VLD_IE
VLD_CTL
VLD_INP_ADR
VLD_INP_CNT
VLD_MBH_ADR
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Value
Rev. 2 — 1 December 2004
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Description
Logic ‘1’ indicates VLD encountered an illegal Huffman code or an
unexpected start code. Refer to
details on the error handling procedure.
This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates VLD encountered 0x000001 while executing
current command.
This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates successful completion of current command.
This bit is cleared by issuing a new command.
-
Each of these bits enables the matching bit from the VLD_STATUS
reg 0x010 to issue an IR to the CPU.
When CPU writes 1 into this field, VLD copies the value of
slice_start_code into its internal register. CPU should do this only
when the VLD is stopped. This bit is always read as 0.
Slice start code when the VLD is restarted; the
slice_start_code_strobe bit field must be set to ‘1’ in order to update
this field.
When this bit is ‘0’, VLD sets the DMA_INPUT_DONE flag (in
VLD_MC_STATUS register) when the DMA_INP_CNT transitions
from non-zero to zero.
When this bit is ‘1’, the same flag is set only with the additional
condition that both highway input buffers are empty.
The slice_start_code_strobe bit field must be set to ‘0’ in order to
update this field)
Force the VLD to operate in Little Endian mode when ‘1’. When set
to ‘0’ the VLD operates in Big Endian mode. The
slice_start_code_strobe bit must be set to ‘0’ in order to update this
bit.
Memory address from which VLD is reading (updated when DMA
read transfer is completed). Must be 32-bit word aligned.
Number of bytes to be read from main memory
Memory address to which the VLD writes macroblock headers when
VLD_CTL[1] is set. Must be 32-bit word aligned.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Section 3.4 Error Handling
PNX15xx Series
for
21-18