PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 60

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 29: VIP and FGPI Timing
Table 30: 10/100 LAN MII Timing
12NC 9397 750 14321
Product data sheet
Symbol
F
F
T
T
Symbol
F
F
T
T
T
VIP
FGPI
SU-CLK
H-CLK
LAN_CLK
CLK
CLK-DV
SU-CLK
H-CLK
Parameter
VDI_CLK1 frequency
VDI_CLK2 frequency
Input setup time
Input hold time
Parameter
LAN_CLK frequency
LAN_TX_CLK and LAN_RX_CLK frequency
Clock to LAN Outputs
Input setup time
Input hold time
8.5 VIP and FGPI Interfaces
8.6 10/100 LAN In MII Mode
[28-4]
[28-5]
[29-1]
[29-2]
[29-3]
[29-4]
[30-1]
[30-2]
[30-3]
Figure 13: VIP and FGPI I/O Timing
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. These inputs are assumed asynchronous.
Maximum frequency may get reduced by the wide spread of propagation delay depending
on the application needs, i.e. input setup/hold time requirements of the receiving device.
Notes:
1. Timing applies whether the clock is external or internal.
2. Timing applies whether the data is output on a positive or a negative edge.
3. See timing measurement conditions
Notes:
1. Timing applies whether the clock is external or internal.
2. Timing applies whether the data is output on a positive or a negative edge.
Rev. 2 — 1 December 2004
VDI_D[33:0]
VDI_V[1:0]
VDI_CLK
Figure
Min
3
2
Min
6
5
3
T
SU-CLK
13.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 1: Integrated Circuit Data
valid
Max
81
100
Max
60
25
17
T
PNX15xx Series
H-CLK
Units
MHz
MHz
ns
ns
Units
MHz
MHz
ns
ns
ns
Notes
1, 2, 3
1, 2, 3
Notes
1, 2, 3
1, 2, 3
1, 2, 3
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