PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 400

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
12NC 9397 750 14321
Product data sheet
Bit
29:12
11:0
Offset 0x10 E1F8
31:3
2:0
Offset 0x10 E1FC
31
30:28
27:16
15:12
11:0
Layer & Mixer Registers
The structure of each layer function block is identical. The register for a function such as Source Address in Layer 1, has the
same structure as the corresponding register in Layer 2. Layer one starts at offset 0x200 from the QVCP base address.
Layer two starts at offset 0x400 from the QVCP base address.
Offset 0x10 E200
31:28
27:0
Offset 0x10 E204
31:23
22:0
Offset 0x10 E208
31:23
12:0
Offset 0x10 E20C
31:28
Symbol
Unused
reload_line
Unused
Field_ID
O_E_STAT
Unused
STG_Y_POS
Unused
STG_X_POS
Unused
Layer N Source Address
A
Unused
Layer N Pitch A
Unused
Layer N Source Width
Unused
Field_
XY_
Layer Source Address A (Packed/Semi Planar Y)
Layer Source Pitch A (Packed/Semi Planar Y)
Layer Source Width (Packed/Semi Planar Y)
Layer Source Address B (Packed/Semi Planar Y)
…Continued
Position
Info
Acces
s
R
R/W
R
R
R
R
R/W
R/W
R/W
0
0
-
-
0
-
-
-
-
-
0
-
0
-
0
-
Value
Rev. 2 — 1 December 2004
Description
line count number where shadow reload occurs.
Please make sure reload line is set to a position earlier than layer
start Y position given in 0x10,E230.
Field_ID is reset by disabling the screen timing generator
Field_ID is incremented with each rising edge of VSYNC and wraps
around after reaching the value 0x7 which yields a sequence of 8
fields which could be differentiated by using the Field_ID register.
Odd/Even flag status (interlaced mode)
Current vertical position of screen timing generator
Current horizontal position of screen timing generator
Layer N Source Data Start Address A in bytes. This sets starting
address A for data transfers from the linear Frame Buffer memory to
Layer N. For semi planar and planar modes this address points to
the Y plane.
Note: It should be aligned on a 128-byte boundary for memory
performance reasons. It has to be 8-byte aligned.
Layer N Source Data Pitch B in bytes. This sets pitch A for data
transfers from the linear Frame Buffer memory to Layer N. For semi
planar and planar modes this determines the pitch for the Y plane.
The value has to be rounded up to the next 64-bit word.
Layer N source width in bytes. For semi planar and planar modes
this determines the source data with in bytes for the Y plane. The
value has to be rounded up to the next 64-bit word.
0 = First field (odd/top field)
1 = Second field (even/bottom field)
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
11-54