PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 460

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 1: Module signal pins
12NC 9397 750 14321
Product data sheet
Signal
fgpo_stop
or
fgpo_buf_start
fgpo_data
fgpo_interrupt
Type
output
output
output
2.1 Stopping clk_fgpo for output flow control
2.2 Reset
2.3 Base Addresses
Some users may wish to supply the FGPO clock externally. The Clock Module can be
set up to receive the clock on VDO_C2 and drive clk_fgpo with that signal. This would
allow the external world to stop the FGPO clock (when low) for flow control. All FGPO
registers can be accessed (read/write) while clk_fgpo is inactive without any bus
time-outs.
FGPO is reset by any PNX15xx Series system reset or by setting the
SOFTWARE_RESET bit FGPO_SOFT_RST register.
Remark: SOFTWARE_RESET does not reset MMIO bus interface registers. Any
DMA transfers will be aborted during a SOFTWARE_RESET. All registers reset to the
Reset Value shown in the Register Description section.
Two base address registers are used to point to main memory buffers in a double
buffering scheme. Addresses are forced into 32-bit address alignment.
…Continued
Description
To External PAD VDO_D[33] via Output Router.
Message Passing Mode:
A programmable pulse on fgpo_stop indicates the end of a message. This pulse may be
programmed to be a one clock pulse concurrent with the last data sample, or a pulse lasting
as long as valid data samples are output.
Record Capture Mode:
A programmable pulse on fgpo_buf_start indicates the start of a new buffer. The pulse may
be programmed to occur one clock before or at the same clock with the first valid data sample
for the buffer
or
A positive pulse lasting as long as each buffer is active.
or
A positive pulse lasting as long as buffer 2 is active.
To External PAD VDO_D[31:0] via Output Router.
General Purpose high speed sample data output changing on each active edge of clk_fgpo.
In 8-bit mode data is placed on fgpo_data7:0]. In 16-bit mode data is placed on
fgpo_data[15:0].
Interrupt status connects to the TriMedia Processor in the PNX15xx Series.
Rev. 2 — 1 December 2004
Chapter 13: FGPO: Fast General Purpose Output
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
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