PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 93

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 6: Video/Data Input Operating Modes
12NC 9397 750 14321
Product data sheet
mode
VDI_MODE[1:0] = 0x0 (Default
after reset)
VDI_MODE[1:0] = 0x1
VDI_MODE[1:0] = 0x2
VDI_MODE[1:0] = 0x3
9.2 Video/Data Output Router
The operating modes of the video/data input router are set by the VDI_MODE MMIO
register. A subset of the operating modes are presented in
656 digital video source with streaming data inputs. A complete behavior of the
output router is available in
features, while
In addition to controlling the operating mode of the VDI pins, VDI_MODE[7] bit
controls the activation of a pre-processing module for the 8-bit data that is routed to
the FGPI module. When VDI_MODE[7] = ‘1’ then the input router scans the lower
VDI_D[7:0] inputs for SAV/EAV codes as defined in the video CCIR 656 standard and
uses the ‘start’ and ‘stop’ signals that are routed to the FGPI module as a line and
field detector. FGPI can then be programmed to store in DRAM each field or line at a
specific location which eases the software processing of the data. This processing
stage allows to use of FGPI as a second Video Input as long as ‘on the fly’ pixel
processing is not required.
A subset of the VDI pins can individually be set to operate as GPIO pins in case they
are not used for their primary video/streaming data function.
The output router can provide certain combinations of the following functions:
1.
•
•
•
VIP function
8- or 10-bit ITU 656 with additional H&V
synchronization signals
or
8- or 10-bit raw data
20-bit ITU 656 as for HD video with additional
H&V synchronization signals
8-bit ITU 656
or
8-bit raw data
n/a
Refresh a TFT LCD display up to W-XGA (1280*768) at 60 Hz with RGB 18/24-
bit per pixel.
Refresh progressive or interlaced standard definition video screens using ITU
656 with YUV4:2:2 or 4:4:4 data, with each screen receiving pixels resulting from
the composition and processing of two display surfaces stored in DRAM.
Refresh of a single high-definition
PNX15xx Series does not have the bandwidth and processing power to do a full HDTV decode/
process and HD display, but it can refresh a HD screen and present graphics and video windows
on such a screen.
Section 9.3
Rev. 2 — 1 December 2004
presents some of the FGPI capabilities.
Section 7. on page
1
or VGA resolution screen.
3-16.
FGPI function
up to 22-bit data capture.
FGPI is usually set in 16- or 32-bit mode
storing into main memory respectively
16- or 32-bit words
up to 12-bit data capture.
FGPI can be set in 8-, 16-, or 32-bit mode
storing into main memory respectively 8-,
16-, or 32-bit words
up to 24-bit data capture
FGPI is usually set in 32-bit mode storing
32-bit words into main memory.
32-bit data capture.
FGPI is usually set to 32-bit mode.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Section 7.2
PNX15xx Series
Table
Chapter 2: Overview
summarizes the VIP
6, which combines
2-19