PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 557

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.2.2 SPDI_STATUS Register Functions
3.2.3 LOCK and UNLOCK State Behavior
3.2.4 UNLOCK Error Behavior and DMA
The UCBITS bit indicates that a complete set of user data and channel status bits is
available in the SPDI_CBITSx and SPDI_UBITSx registers. This bit is updated on a
block basis.
The LOCK bit indicates whether the interface has locked onto the incoming SPDIF
stream. Software must detect the lock condition asserted before enabling data
capture. The LOCK bit is active as long as an oversampling clock is supplied. Capture
does not have to be enabled for the LOCK bit to be active.
The UNLOCK bit indicates that the receiver has either: 1) Not attained the locked
state -or- 2) Has fallen out of the locked state for some reason. At power on, the
interface will indicate that it is NOT locked by asserting the UNLOCK status bit.
During normal operation, when a valid SPDIF input stream is applied to the pin
interface, the receiver will indicate a lock condition is attained by asserting the LOCK
bit. If the receiver then looses lock, the UNLOCK bit will be asserted. Each of the
UNLOCK and LOCK status bits can be used to generate an interrupt to the system.
Note that the LOCK and UNLOCK status bits are sticky, meaning that once they are
set in the status register, each must be cleared explicitly by writing to the appropriate
bit in the SPDI_INTCLR register.
The VERR and PERR bits indicate validity and parity error conditions associated with
the data contained within the input stream. Note that when validity errors occur, the
associated payload data is passed unchanged. When parity errors occur, the
associated payload data is muted (zeroed). This conditions apply to all modes except
raw mode capture. For raw mode, the entire decoded subframe is passed to memory
regardless of parity.
OVERRUN and HBE indicate data loss conditions in memory and internally to the
hardware. BUF1_ACTIVE indicates whether memory buffer 1 is currently being filled
with data. BUF1_FULL and BUF2_FULL indicate whether memory buffers are
completely used. Refer to
Shortly after power on (or any reset), the receiver will indicate that it is not locked to
an input stream by asserting the UNLOCK bit in SPDI_STATUS. Later, once a valid
SPDIF input stream is applied to the interface, the receiver will assert the LOCK
status bit. At this moment, the receiver has determined that the input stream is valid
and that DMA capture can be started by the user. Note that these two status bits,
LOCK and UNLOCK are sticky and may become activated regardless of the state of
the SPDIF Input capture enable bit SPDI_CTL.CAP_ENABLE. Software must
explicitly clear the LOCK and UNLOCK status bits using the appropriate
SPDI_INTCLR register bits. The SPDIF Input receiver will never be in a locked state
and in an unlocked state simultaneously. Also note that the LOCK and UNLOCK
behavior applies to all capture modes. For raw mode processing, parity and validity
bits are ignored. PERR or VERR status bits are not updated.
If the receiver should encounter an error condition in the stream, it will indicate this by
asserting the UNLOCK bit. During runtime, the conditions that can cause the
UNLOCK state are: 1) an unexpected bi-phase error is encountered; 2) the input
Rev. 2 — 1 December 2004
Table 6
for more details.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 18: SPDIF Input
18-8