PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 738

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
6.7 Cache coherency
Because the device driver can produce descriptors with write-only operations and
consume the status fields with read-only operations, transfers can be made “cache
safe,” and descriptors can be packed together in cache blocks and cached. Status
words can also be packed together. The device driver must take care of cache
coherency if cache coherency is not enforced by a snooping cache in the host
processor.
If the device driver doesn’t own all of the status words in a cache block that contains
multiple status words, then the Ethernet hardware may be writing to a status field in
memory while that status is also included in a cache block loaded in the host
processor’s cache, causing the values for that status in the host cache to be stale.
This can be solved by invalidating these cache blocks and causing them to be read
again from the host memory whenever the device driver receives ownership of these
status words, that is, when the Tx(Rt)ConsumeIndex or RxProduceIndex are
updated.
Before updating the Tx(Rt)ProduceIndex or RxConsumeIndex, the device driver must
make sure the associated descriptors are written back from the cache to the memory
so that the new descriptor values become visible to the Ethernet hardware. When
flushing these cache blocks, care must be taken not to modify the fields of descriptors
that are already owned by the Ethernet hardware.
Alternatively, the device driver can use non-cached memory traffic for the descriptors
and statuses. In that case, there is no need to worry about cache coherency,
however, a higher amount of memory traffic may be required for the descriptors and
status words.
•
Packet transmission can cause errors including LateCollision,
ExcessiveCollision, ExcessiveDefer, NoDescriptor, and Underrun. These errors
are reported back in the transmission status word and in the interrupt status
register. For more information refer to
Rev. 2 — 1 December 2004
Chapter 23: LAN100 — Ethernet Media Access Controller
Section 4.2
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
and
PNX15xx Series
Section
5.4.
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