PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 424
PNX1501E
Manufacturer Part Number
PNX1501E
Description
Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1501E.pdf
(819 pages)
Specifications of PNX1501E
Product
DSPs
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-795
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
Details
Other names
PNX1501E,557
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Philips Semiconductors
Volume 1 of 1
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Product data sheet
Figure 3:
Digital Video Input Port Timing Relationships in HD Mode
Channel A
Channel B
2.2.2 Input Timing
DV_VALID
2.3 Test Pattern Generator
UV_BUS
Y_BuS
CLK
A separate signal, dv_valid, is provided to validate all incoming data. The relationship
between dv_valid and data, with reference to clock, is shown in
The Test Pattern Generator produces a video stream with a pixel frequency of half the
VIP input clock e.g., the 27 MHz encoder clock by programming the clock selection
block accordingly.
The sync generation is NTSC-like, with 525 lines per frame and 858 pixels per line.
The active video range is 720x462 bordered by a white frame.
The test pattern is shown in
–
–
–
–
–
–
–
–
U0
Y0
A white 2-pixel wide frame—size 720x462
A color bar—white 100%, yellow 75%, cyan 75%, green 75%, magenta 75%,
red 75%, blue 75%, and black 0%.
A grey ramp—full value range 0–255
A vertical multiburst
A horizontal multiburst—first rectangle solid in odd, second solid in even field
Vertical lines
A moving cursor
Test pattern
Rev. 2 — 1 December 2004
Y1
V0
Y2
U1
Figure
4, and contains the following elements:
Y3
V1
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Y4
U2
PNX15xx Series
Figure
Y5
V2
3.
12-4
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