PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 621

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.1.6 PatRam
Table 4: Color BLT Parameters
Simple Screen-to-Screen BLTs use four registers to initiate the operation: SrcXY/
SrcLinear, DstXY/DstLinear, BltCtl, and BltSize. This assumes that the stride
registers have already been initialized with the current screen pitch.
Simple Color Host-to-Screen BLTs use four registers to initiate the operation: DstXY/
DstLinear, SrcXY/SrcLinear, BltCtl, and BltSize. This assumes that the DstStride
register has already been initialized with the current screen pitch.
The SrcXY/SrcLinear register specifies the data alignment at the start of each
scanline. The first
least significant bytes. Each scanline of host data is padded to end on a
boundary. The Engine will draw BltSize.Width pixels for each scanline of the BLT. The
number of
((BltSize.Width + (SrcLinear & 3) )*(PSize/8) + 3)/4
Advanced BLTs will initialize a small group of additional registers. If transparency is
desired, the Color Compare Color and Transparency Mask registers are loaded.
If patterns are used, the DstXY register and the PatRam (see below) must be loaded.
The pattern is usually tiled to the screen assuming the upper left corner of the pattern
is anchored to the upper left corner of the screen. To easily do this, the three low bits
of the X and Y fields of the DstXY register are used to derive the initial alignment of
the pattern data. The pattern register can be “un-anchored” by first writing to the
DstXY register to specify the pattern alignment, then writing the DstLinear with the
actual destination screen address. The last write to the DstXY register will set the
pattern alignment. This means that you must always load the DstXY register before
starting a BLT that uses the pattern.
The PatRam is an 8*8 pixel pattern cache that provides pattern data for the ROP
ALU. The PatRam operates at either 8, 16, or 32 bits per pixel as specified in the
PSize register:
In 8 bit per pixel mode, only the first 64 bytes of the PatRam are used. The host must
initialize bytes 0 to 63 prior to initiating a BLT that uses a pattern. In this mode, byte 0
of the PatRam is the upper left pixel in the ram.
In 16 bit per pixel mode, only the first 128 bytes of the PatRam are used. The host
must initialize bytes 0 to 127 prior to initiating a BLT that uses a pattern. In this mode,
bytes 0 and 1 of the PatRam are the upper left pixel in the ram. Byte 0 is the LSB of
the pixel and contains five bits of the blue component and three bits of the green
component. Byte 1 contains the remaining bits of the green component and five bits
of the red component.
Parameters
TransMask
BltCtl
BltSize
DWORD
Description
The transparency mask is used to mask out bits for color compare
operations.
drawing function: ROP type, color compare enables, source data path
Specifies destination width and height, initiates drawing function.
Rev. 2 — 1 December 2004
s of host data for each scanline is
DWORD
of data will have (SrcLinear & 3) pixels of pad data in the
…Continued
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 20: 2D Drawing Engine
PNX15xx Series
DWORD
20-12