AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1005

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.7.9
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in
1029.
• PTRCS: PDCA Transfer Request Comparison Selection
• PTRM: PDCA Transfer Request Mode
Table 33-6.
• UPDM: Synchronous Channels Update Mode
32117C–AVR-08/11
UPDM
0
1
2
31
23
15
–
7
–
-
Selection of the comparison used to set the WRDY bit and the corresponding PDCA transfer request.
0: Manual write of double buffer registers and manual update of synchronous channels. The update occurs at the beginning of
the next PWM period, when the UPDULOCK bit in
1: Manual write of double buffer registers and automatic update of synchronous channels. The update occurs when the Update
Period is elapsed.
2: Automatic write of duty-cycle update registers by the PDCA and automatic update of synchronous channels. The update
occurs when the Update Period is elapsed.
3: Reserved.
Sync Channels Mode Register
WRDY bit and PDCA Transfer Request
PTRM
x
x
0
1
PTRCS
30
22
14
–
6
–
-
SCM
Read/Write
0x020
0x00000000
WRDY bit and PDCA Transfer Request
The WRDY bit in
never set to 1.
The WRDY bit in
period is elapsed, the PDCA transfer is never requested.
The WRDY bit in
as soon as the update period is elapsed.
The WRDY bit in
as soon as the selected comparison matches.
29
21
13
–
5
–
-
”Interrupt Status Register 2” on page 1013
”Interrupt Status Register 2” on page 1013
”Interrupt Status Register 2” on page 1013
”Interrupt Status Register 2” on page 1013
PTRM
28
20
12
–
4
–
-
”Sync Channels Update Control Register” on page 1007
SYNC3
27
19
11
–
3
-
-
SYNC2
26
18
10
–
2
-
-
”Write Protect Status Register” on page
and the PDCA transfer request are
is set to 1 as soon as the update
and the PDCA transfer is requested
and the PDCA transfer is requested
SYNC1
25
17
9
–
1
-
AT32UC3C
UPDM
is set.
SYNC0
24
16
8
–
0
-
1005