AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 813

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.8.1
Name:
Access Type:
Offset:
Reset Value:
The Control Register should only be written to enable the IISC after the chosen configuration has been written to the Mode
Register, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR
register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR.
• SWRST: Software Reset
• TXDIS: Transmitter Disable
• TXEN: Transmitter Enable
• CKDIS: Clocks Disable
• CKEN: Clocks Enable
• RXDIS: Receiver Disable
• RXEN: Receiver Enable
32117C–AVR-08/11
SWRST
31
23
15
7
-
-
-
Writing a zero to this bit has no effect.
Writing a one to this bit resets all the registers in the module. The module will be disabled after the reset.
This bit always reads as zero.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC Transmitter. SR.TXEN will be cleared when the Transmitter is effectively stopped.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC Transmitter, if TXDIS is not one. SR.TXEN will be set when the Transmitter is effectively
started.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC clocks generation.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC clocks generation, if CKDIS is not one.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the IISC Receiver. SR.TXEN will be cleared when the Transmitter is effectively stopped.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the IISC Receiver, if RXDIS is not one. SR.RXEN will be set when the Receiver is effectively
started.
Control Register
30
22
14
CR
Write-only
0x00
0x00000000
6
-
-
-
-
TXDIS
29
21
13
5
-
-
-
TXEN
28
20
12
4
-
-
-
CKDIS
27
19
11
3
-
-
-
CKEN
26
18
10
2
-
-
-
RXDIS
25
17
9
1
-
-
-
AT32UC3C
RXEN
24
16
8
0
-
-
-
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