AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 817

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.8.3
Name:
Access Type:
Offset:
Reset Value:
• TXURCH: Transmit Underrun Channel
• RXORCH: Receive Overrun Channel
• TXUR: Transmit Underrun
• TXRDY: Transmit Ready
• TXEN: Transmitter Enabled
• RXOR: Receive Overrun
• RXRDY: Receive Ready
• RXEN: Receiver Enabled
32117C–AVR-08/11
31
23
15
7
-
-
This field is cleared when SCR.TXUR is written to one
Bit i of this field is set when a transmit underrun error occurred in channel i (i=0 for first channel of the frame)
This field is cleared when SCR.RXOR is written to one
Bit i of this field is set when a receive overrun error occurred in channel i (i=0 for first channel of the frame)
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an underrun error occurs on the THR register or when the corresponding bit in SSR is written to one
This bit is cleared when data is written to THR
This bit is set when the THR register is empty and can be written with new data to be transmitted
This bit is cleared when the Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request
This bit is set when the Transmitter is effectively enabled, following a CR.TXEN request
This bit is cleared when the corresponding bit in SCR is written to one
This bit is set when an overrun error occurs on the RHR register or when the corresponding bit in SSR is written to one
This bit is cleared when the RHR register is read
This bit is set when received data is present in the RHR register
This bit is cleared when the Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request
This bit is set when the Receiver is effectively enabled, following a CR.RXEN request
Status Register
TXUR
30
22
14
SR
Read-only
0x08
0x00000000
6
-
TXURCH[3:0]
TXRDY
29
21
13
5
-
TXEN
28
20
12
4
-
RXORCH
27
19
11
3
-
-
RXOR
26
18
10
2
-
TXURCH[7:4]
RXRDY
25
17
9
1
-
AT32UC3C
RXEN
24
16
8
0
-
817