AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 626
AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2256C-A2UR
Manufacturer:
Cirrus
Quantity:
48
Part Number:
AT32UC3C2256C-U
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
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Manufacturer:
ATMEL
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Company:
Part Number:
AT32UC3C2256C-Z2UR
Manufacturer:
ATMEL
Quantity:
93
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32117C–AVR-08/11
RSTNACK: Reset Non Acknowledge
RSTIT: Reset Iterations
SENDA: Send Address
STTTO: Start Time-out
STPBRK: Stop Break
STTBRK: Start Break
RSTSTA: Reset Status Bits
TXDIS: Transmitter Disable
TXEN: Transmitter Enable
RXDIS: Receiver Disable
RXEN: Receiver Enable
RSTTX: Reset Transmitter
RSTRX: Reset Receiver
0: No effect
1: Resets NACK in CSR.
0: No effect.
1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled.
0: No effect.
1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set.
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR.
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No
0: No effect.
1: Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE, LINSNRE and RXBRK in CSR.
0: No effect.
1: Disables the transmitter.
0: No effect.
1: Enables the transmitter if TXDIS is 0.
0: No effect.
1: Disables the receiver.
0: No effect.
1: Enables the receiver, if RXDIS is 0.
0: No effect.
1: Resets the transmitter.
0: No effect.
1: Resets the receiver.
effect if no break is being transmitted.
effect if a break is already being transmitted.
AT32UC3C
626
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