AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 697

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27. Two-wire Master Interface (TWIM)
27.1
27.2
32117C–AVR-08/11
Features
Overview
Rev.: 1.1.0.1
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The Atmel Two-wire Master Interface (TWIM) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD
controller, and temperature sensor, to name a few. The TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus
is performed internally and relinquishes the bus automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Master Mode and a full I²C compatible device.
Table 27-1.
Note:
I²C
Standard-mode (100 kbit/s)
Fast-mode (400 kbit/s)
Fast-mode Plus (1 Mbit/s)
7- or 10-bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope Control and Input Filtering (Fast mode)
Clock Stretching
Compatible with I
Compatible with SMBus standard
Compatible with PMBus
Compatible with Atmel Two-wire Interface Serial Memories
DMA interface for reducing CPU load
Arbitrary transfer lengths, including 0 data bytes
Optional clock stretching if transmit or receive buffers not ready for data transfer
– Multi-master support
– Transfer speeds of 100 and 400 kbit/s
– 7- and 10-bit and General Call addressing
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
Standard
1. START + b000000001 + Ack + Sr
(1)
Atmel TWIM Compatibility with I²C Standard
²
C standard
Table 27-1
lists the compatibility level of the Atmel Two-wire Interface in
Atmel TWIM
Supported
Supported
Supported
Supported
Not Supported
Supported
Supported
Supported
Supported
AT32UC3C
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