AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 569

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.1.3
Figure 25-3. Fractional Baud Rate Generator
25.6.1.4
32117C–AVR-08/11
CLK_USART/DIV
CLK
CLK_USART
Reserved
Fractional Baud Rate in Asynchronous Mode
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
1
2
3
0
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in BRGR.
Baudrate
Error
BaudRate
16-bit Counter
CD
=
=
---------------------------------------------------------------- -
⎛
⎝
1
8 2 Over
Modulus
–
=
Control
(
⎛
⎝
FP
SelectedClock
------------------------------------- -
ExpectedBaudRate
-------------------------------------------------- -
SelectedClock
–
ActualBaudRate
CD
) CD
⎛
⎝
+
glitch-free
USCLKS = 3
FP
------ -
logic
FP
8
⎞
⎠
⎞
⎠
SYNC
⎞
⎠
0
>1
CD
0
1
0
1
OVER
Sampling
Divider
FIDI
AT32UC3C
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
569