AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 490

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.2
24.5.3
Table 24-1.
32117C–AVR-08/11
31:2
Bit
31
30
29
1
0
FIFO
Receive Buffers
Address of beginning of buffer
Wrap - marks last descriptor in receive buffer descriptor list.
Ownership - needs to be zero for the MACB to write data to the receive buffer. The MACB sets this to one once it has
successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
Global all ones broadcast address detected
Multicast hash match
Unicast hash match
Receive Buffer Descriptor Entry
FIFO depths are 124 bytes.
Data is typically transferred in and out of the FIFOs in bursts of four words. In reception, a bus
request is asserted when the FIFO contains four words and has space for three more. For trans-
mission, a bus request is generated when there is space for four words, or when there is space
for two words if the next transfer is only one or two words.
Thus the bus latency is less than the time it takes to load the FIFO and transmit or receive three
words (12 bytes) of data.
At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six PB clock
cycles should be allowed for data to be loaded from the bus and to propagate through the
FIFOs. For a 60 MHz PB clock this takes 100 ns, making the bus latency requirement 860 ns.
Received frames, optionally including CRC/FCS, are written to receive buffers stored in mem-
ory. Each receive buffer size is 128 bytes. The start location for each receive buffer is stored in
memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue
pointer register. The receive buffer start location is a word address. For the first buffer of a
frame, the start location can be offset by up to three bytes depending on the value written to bits
14 and 15 of the network configuration register. If the start location of the buffer is offset the
available length of the first buffer of a frame is reduced by the corresponding number of bytes.
Each list entry consists of two words, the first being the address of the receive buffer and the
second being the receive status. If the length of a receive frame exceeds the buffer length, the
status word for the used buffer is written with zeroes except for the “start of frame” bit and the
offset field, if appropriate. Bit zero of the address field is written to one to show the buffer has
been used. The receive buffer manager then reads the location of the next receive buffer and
fills that with receive frame data. The final buffer descriptor status word contains the complete
frame status. Refer to
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
Table 24-1
Word 0
Word 1
for details of the receive buffer descriptor list.
Function
AT32UC3C
490