AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 886

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6.2.14
32117C–AVR-08/11
Management of IN endpoints
• Overview
TXINI
FIFOCON
TXINI
FIFOCON
IN packets are sent by the USBC device controller upon IN requests from the host.
The endpoint and its descriptor in RAM must be pre configured (see section
ment” on page 881
When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set
simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable
(TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt. This has no effect on the endpoint FIFO.
The user writes the IN data to the bank referenced by the EPn descriptor and allows the USBC
to send the data by writing a one to the FIFO Control Clear (UECONnCLR.FIFOCONC) bit. This
will also cause a switch to the next bank if the IN endpoint is composed of multiple banks. The
TXINI and FIFOCON bits will be updated accordingly.
TXINI should always be cleared before clearing FIFOCON to avoid missing an TXINI event.
Figure 32-11. Example of an IN endpoint with one data bank
Figure 32-12. Example of an IN endpoint with two data banks
SW
write data to CPU
SW
write data to CPU
BANK 0
NAK
BANK 0
for more details).
SW
IN
SW
SW
IN
write data to CPU
BANK 1
(bank 0)
DATA
(bank 0)
DATA
SW
HW
ACK
HW
ACK
SW
write data to CPU
IN
SW
write data to CPU
BANK0
BANK 0
AT32UC3C
(bank 1)
DATA
”RAM manage-
SW
ACK
IN
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