AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 584

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 25-22. Timeguard Operations
25.6.3.11
32117C–AVR-08/11
Baud Rate
TXEMPTY
TXRDY
Clock
Write
THR
TXD
Receiver Time-out
Start
Bit
D0
D1
Table 25-8
in relation to the function of the Baud Rate.
Table 25-8.
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of
frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the
Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at
0. Otherwise, the receiver loads a counter with the value programmed in TO. This counter is
decremented at each bit period and reloaded each time a new character is received. If the coun-
ter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:
D2
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on
RXD before a new character is received will not provide a time-out. This prevents having to
D3
D4
D5
Baud Rate
indicates the maximum length of a timeguard period that the transmitter can handle
115200
Bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
D6
Maximum Timeguard Length Depending on Baud Rate
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
Bit time
69.4
52.1
34.7
29.9
17.9
17.4
D1
833
104
8.7
µs
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Timeguard
AT32UC3C
212.50
17.71
13.28
26.56
8.85
7.63
4.55
4.43
2.21
ms
TG = 4
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