AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 500

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.16
24.5.17
32117C–AVR-08/11
PHY Maintenance
Media Independent Interface
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame.
The reserved value of 0x0000 for wake-on LAN target address value will not cause an ARP
request event, even if matched by the frame.
A specific address 1 filter match event will occur if all of the following are true:
A multicast filter match event will occur if all of the following are true:
The register MAN enables the MACB to communicate with a PHY by means of the MDIO inter-
face. It is used during auto-negotiation to ensure that the MACB and the PHY are configured for
the
The PHY maintenance register is implemented as a shift register. Writing to the register starts a
shift operation which is signalled as complete when bit two is set in the network status register
(about 2000 CLK_MACB_PB) cycles later when bit ten is set to zero, and bit eleven is set to one
in the network configuration register). An interrupt is generated as this bit is set. During this time,
the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with
each Divided PB Clock (DPC) cycle. This causes transmission of a PHY management frame on
MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of
management operation, the bits have shifted back to their original locations. For a read opera-
tion, the data bits are updated with data read from the PHY. It is important to write the correct
values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read
clause 45 PHYs, bits [31:28] should be written to 0x0011. For a description of DPC generation,
see the network configuration register in section
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the
USRIO register controls the interface that is selected. When this bit is set, the RMII interface is
selected, else the MII interface is selected.
• the frame has a broadcast destination address (bytes 1 to 6)
• the frame has a typeID field of 0x0806 (bytes 13 and 14)
• the frame has an ARP operation field of 0x0001 (bytes 21 and 22)
• the least significant 16 bits of the frame ARP target protocol (bytes 41 and 42) match the
• specific address 1 events are enabled by WOL.SA1 bit
• the frame destination address matches the value programmed in the specific address 1
• multicast hash events are enabled by WOL.MTI bit
• multicast hash filtering is enabled by NCFG.MTI bit
• the frame destination address matches against the multicast hash filter
• the frame destination address is not a broadcast
value written in WOL.IP.
registers
same speed and duplex configuration.
”Network Configuration Register” on page
AT32UC3C
509.
500