AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 709

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 27-13. Combining a Read and Write Transfer
27.8.8
27.8.8.1
Figure 27-14. A Write Transfer with 10-bit Addressing
27.8.8.2
32117C–AVR-08/11
SR.IDLE
RXRDY
TXRDY
TWD
RHR
THR
Ten Bit Addressing
S
Master Transmitter
Master Receiver
SADR
S
1
R
SLAVE ADDRESS
1
To generate this transfer:
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In
white boxes are driven by the slave.
To perform a master transmitter transfer:
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
1
TWI_RHR
Figure 27-14
1st 7 bits
A
Read
1
desired address and NBYTES value.
0
DATA0
X
X
and
RW A1
0
DATA0
A
Figure
DATA1
SLAVE ADDRESS
27-15, the grey boxes represent signals driven by the master, the
2nd byte
DATA3
A
Sr
DADR
A2
1
DATA
W
A
A
DATA2
DATA2
DATA
A
AA
AT32UC3C
P
DATA3
DATA3
NA
P
709
2