AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 317

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32117C–AVR-08/11
•Write cycle
Figure 18-11. Write Cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
Similarly,
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time
and NCS (write) hold times as:
And,
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
CLK_SMC
NWE
NCS
NWECYCLE
NCSWRHOLD
NCSWRSETUP
NWECYCLE
NWEHOLD
NWESETUP
=
=
NCSWRSETUP
=
=
NWECYCLE NCSWRSETUP
NWECYCLE NWESETUP
NWESETUP
NCSWRPULSE
NWEPULSE
NWECYCLE
+
+
NCSWRPULSE
NWEPULSE
+
NWEPULSE
+
NWEHOLD
NCSWRPULSE
NCSWRHOLD
NWEHOLD
NCSWRHOLD
AT32UC3C
317

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