SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 115

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.3
ARM DDI 0165B
Maximum interrupt latency
The processor samples the interrupt input pins on the rising-edge of the system clock,
CLK. The sampled signal is examined and can cause an interrupt in the following cases:
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•
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•
If the sampled signal is asserted at the same time as a multicycle instruction has started
its second or later cycle of execution, the interrupt exception entry does not start until
the instruction has completed.
The worst-case interrupt latency occurs when the longest possible
incurs a Data Abort. The processor must enter the Data Abort mode before taking the
interrupt so that the interrupt exception exit can occur correctly. This causes a
worst-case latency of 24 cycles:
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•
•
•
•
•
Whenever a new instruction is scheduled to enter the Execute stage of the
pipeline.
Whenever a new instruction is in the Execute stage for the first cycle of its
execution. Here cycle refers to CLK cycles with CLKEN HIGH.
Whenever a coprocessor instruction is being busy waited in the Execute stage.
Whenever a new instruction which interlocked in the Execute stage has just
progressed to its first active Execute cycle.
The longest
Counting the first Execute cycle as 1, the
The last word to be transferred by the
status for the transfer is returned in this cycle.
If a Data Abort happens, the processor detects this in cycle 18 and prepares for
the Data Abort exception entry in cycle 19.
Cycles 20 and 21 are the Fetch and Decode stages of the Data Abort entry
respectively.
During cycle 22, the processor prepares for FIQ entry, issuing Fetch and Decode
cycles in cycles 23 and 24.
Therefore, the first instruction in the FIQ routine enters the Execute stage of the
pipeline in stage 25, giving a worst-case latency of 24 cycles.
Copyright © 2000 ARM Limited. All rights reserved.
LDM
instruction is one that loads all of the registers, including the PC.
LDM
LDM
is transferred in cycle 17, and the abort
takes 16 cycles.
LDM
instruction
Interrupts
5-7