SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 95

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
This DABORT to DnMREQ, DSEQ, and DMORE path has been removed from the
ARM9E-S design because:
•
•
Due to this modification, the memory system connected to ARM9E-S is responsible for
ignoring a data memory request made during the cycle of an aborted data transfer. This
is necessary to prevent a following memory access from corrupting memory after an
aborted access. The memory system must ignore DnMREQ, DSEQ, and DMORE in
this case.
a combinational input to output path is undesirable in an ASIC design flow
the path is critical in ARM9TDMI.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnRW
DnMREQ
DSEQ
DMORE
DABORT
Address class
signals
WDATA[31:0]
(Write)
Figure 4-5 ARM9TDMI effect of DABORT on following memory access
Write address
Write cycle
(aborted)
Read address
Write data
I cycle
Memory Interface
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