SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 94

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.9
4.9.1
4.9.2
4.9.3
4-18
Data interface data timed signals
WDATA[31:0]
RDATA[31:0]
DABORT
The data timed signals are:
•
•
•
WDATA[31:0] is the write data bus. All data written out from the ARM9E-S is
broadcast on this bus. Data transfers from the ARM9E-S to a coprocessor also use this
bus during C cycles. In normal circumstances, a memory system must sample the
WDATA[31:0] bus on the rising edge of CLK at the end of a write bus cycle. The value
on WDATA[31:0] is valid only during write cycles.
RDATA[31:0] is the read data bus, and is used by the ARM9E-S to fetch data. It is
sampled on the rising edge of CLK at the end of the bus cycle, and is also used during
C cycles to transfer data from a coprocessor to the ARM9E-S.
DABORT indicates that a memory transaction failed to complete successfully.
DABORT is sampled at the end of the bus cycle during active memory cycles (S cycles
and N cycles).
If DABORT is asserted on a data access, it causes the ARM9E-S to take the Data Abort
trap.
DABORT can be used by a memory management system to implement, for example, a
basic memory protection scheme, or a demand-paged virtual memory system.
The ARM9E-S design differs from ARM9TDMI in that ARM9TDMI features a
combinational path from DABORT to DnMREQ, DSEQ, and DMORE. This path is
present so that an aborted memory access can cancel memory accesses requested by
following instructions.
An example of this is shown in Figure 4-5 on page 4-19, where a load instruction
follows an aborted store.
WDATA[31:0]
RDATA[31:0]
DABORT.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B