SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 59

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.8.2
ARM DDI 0165B
The control bits
The Q flag
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
instructions:
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•
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The Q flag is sticky in that, once set by an instruction, it remains set until explicitly
cleared by an
conditionally on the status of the Q flag. To determine the status of the Q flag you must
read the PSR into a register and extract the Q flag from this. For details of how the Q
flag is set and cleared, see individual instruction definitions in the ARM Architectural
Reference Manual.
The bottom eight bits of a PSR are known collectively as the control bits. They are the:
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•
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The control bits change when an exception occurs. When the processor is operating in
a privileged mode, software can manipulate these bits.
Interrupt disable bits
The I and F bits are the interrupt disable bits:
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T bit
Never use an
you do this, the processor enters an unpredictable state.
QADD
QDADD
QSUB
QDSUB
SMLAxy
SMLAWy
Interrupt disable bits
T bit
Mode bits on page 2-18.
when the I bit is set, IRQ interrupts are disabled
when the F bit is set, FIQ interrupts are disabled.
Caution
Copyright © 2000 ARM Limited. All rights reserved.
MSR
MSR
instruction to force a change to the state of the T bit in the CPSR. If
instruction writing to CPSR. Instructions cannot execute
Programmer’s Model
2-17