SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 218

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

AC Parameters
9-10
Symbol
Tiscfg
Tihcfg
Tovdbgack
Tohdbgack
Tovdbgrng
Tohdbgrng
Tovdbgrqi
Tohdbgrqi
Tovdbgstat
Tohdbgstat
Tovdbgcomm
Tohdbgcomm
Tisdbgin
Tihdbgin
Tovdbgsm
Tohdbgsm
Tovtdoen
Tohtdoen
Tovsdin
Tohsdin
Tovtdo
Tohtdo
Tisntrst
Tihntrst
Tistdi
Copyright © 2000 ARM Limited. All rights reserved.
Parameter
Configuration input setup to rising CLK
Configuration input hold from rising CLK
CLK rising to DBGACK valid
DBGACK hold time from CLK rising
CLK rising to DBGRNG valid
DBGRNG hold time from CLK rising
CLK rising to DBGRQI valid
DBGRQI hold time from CLK rising
Rising CLK to debug status valid
Debug status hold from CLK rising
Rising CLK to comms channel outputs valid
Comms channel output hold time from rising CLK
Debug inputs input setup to rising CLK
Debug inputs input hold from rising CLK
CLK rising to debug state valid
Debug state hold from CLK rising
CLK rising to DBGnTDOEN valid
DBGnTDOEN hold from CLK rising
CLK rising to DBGSDIN valid
DBGSDIN hold from CLK rising
CLK rising to DBGTDO valid
DBGTDO hold from CLK rising
DBGnTRST input setup to CLK rising
DBGnTRST input hold from CLK rising
DBGTDI input setup to CLK rising
Table 9-1 Target AC timing parameters (continued)
20%
-
-
>0%
-
>0%
-
>0%
-
>0%
-
>0%
35%
-
-
>0%
-
>0%
-
>0%
-
>0%
25%
-
25%
Min
ARM DDI 0165B
Max
-
0%
60%
-
80%
-
45%
-
30%
-
60%
-
-
0%
30%
-
40%
-
20%
-
35%
-
-
0%
-