SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 205

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.27
ARM DDI 0165B
Cycle
ready
not ready
a. IREQ = InMREQ, ISEQ.
b. DREQ = DnMREQ, DSEQ.
c. P = PASS.
d. LC = LATECANCEL.
Double coprocessor register transfer (from ARM)
1
1
.
n
n+1
n+2
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
The move double to coprocessor (
registers to a coprocessor.
Data is transferred over the data bus interface, in a similar fashion to a store register
operation.
An interrupt can cause the ARM9E-S to abandon a busy-waiting coprocessor
instruction (see Busy-waiting and interrupts on page 6-17).
Coprocessor operations are only available in ARM state.
The
MCRR
IREQ
I cycle
S cycle
I cycle
I cycle
I cycle
I cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction cycle timings are shown in Table 8-34.
a
INSTR
(pc+2i)
-
(pc+3i)
(pc+2i)
-
-
(pc+3i)
-
DA
-
-
-
-
-
-
-
DREQ
C cycle
I cycle
C cycle
C cycle
C cycle
I cycle
I cycle
MCRR
) operation transfers two specified ARM
b
Table 8-34 MCRR instruction cycle timing
WDATA
Rd
Rn
-
-
Rd
Rn
-
P
1
1
1
1
1
1
1
c
LC
0
0
0
0
0
0
0
d
Instruction Cycle Times
CHSD
GO
WAIT
CHSE
LAST
-
WAIT
WAIT
GO
LAST
-
8-45