SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 6

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
vi
Appendix A
Appendix B
Appendix C
Differences Between the ARM9E-S and the ARM9TDMI
Signal Descriptions
A.1
A.2
A.3
A.4
A.5
A.6
B.1
B.2
B.3
B.4
B.5
Debug in depth
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
C.12
C.13
C.14
C.15
Copyright © 2000 ARM Limited. All rights reserved.
Clock interface signals ................................................................................ A-2
Instruction memory interface signals .......................................................... A-3
Data memory interface signals ................................................................... A-4
Miscellaneous signals ................................................................................. A-6
Coprocessor interface signals .................................................................... A-7
Debug signals ............................................................................................. A-8
Interface signals ......................................................................................... B-2
ATPG scan interface .................................................................................. B-5
Timing parameters ...................................................................................... B-6
ARM9E-S design considerations ................................................................ B-7
ARM9E-S debugger considerations ........................................................... B-9
Scan chains and JTAG interface ................................................................ C-2
Resetting the TAP controller ....................................................................... C-5
Instruction register ...................................................................................... C-6
Public instructions ....................................................................................... C-7
Test data registers .................................................................................... C-10
ARM9E-S core clock domains .................................................................. C-17
Determining the core and system state .................................................... C-18
Behavior of the program counter during debug ........................................ C-24
Priorities and exceptions .......................................................................... C-27
EmbeddedICE-RT logic ............................................................................ C-28
Vector catching ......................................................................................... C-39
Single-stepping ......................................................................................... C-40
Coupling breakpoints and watchpoints ..................................................... C-41
Disabling EmbeddedICE-RT .................................................................... C-44
EmbeddedICE-RT timing .......................................................................... C-45
ARM DDI 0165B