SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 32

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Introduction
1-14
Operation
Multiple block
data operations
Store
Multiple block
data operations
Cache hint
Byte signed
Halfword
Halfword signed
Stack operations
Stack operations and restore CPSR
User registers
Load double
Word
Word with User mode privilege
Byte
Byte with User mode privilege
Halfword
Stack operations
User registers
Store double
Prefetch DCache line
Increment before
Increment after
Decrement before
Decrement after
Increment before
Increment after
Decrement before
Decrement after
Copyright © 2000 ARM Limited. All rights reserved.
Assembler
LDR{cond}SB Rd, <a_mode3>
LDR{cond}H Rd, <a_mode3>
LDR{cond}SH Rd, <a_mode3>
LDM{cond}<a_mode4L> Rd{!}, <reglist>
LDM{cond}IB Rd{!}, <reglist>{^}
LDM{cond}IA Rd{!}, <reglist>{^}
LDM{cond}DB Rd{!}, <reglist>{^}
LDM{cond}DA Rd{!}, <reglist>{^}
LDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^
LDM{cond}<a_mode4L> Rd{!}, <reglist>^
LDR{cond}D Rd, <a_mode3>
STR{cond} Rd, <a_mode2>
STR{cond}T Rd, <a_mode2P>
STR{cond}B Rd, <a_mode2>
STR{cond}BT Rd, <a_mode2P>
STR{cond}H Rd, <a_mode3>
STM{cond}<a_mode4S> Rd{!}, <reglist>
STM{cond}IB Rd{!}, <reglist>{^}
STM{cond}IA Rd{!}, <reglist>{^}
STM{cond}DB Rd{!}, <reglist>{^}
STM{cond}DA Rd{!}, <reglist>{^}
STM{cond}<a_mode4S> Rd{!}, <reglist>^
STR{cond}D Rd, <a_mode3>
PLD <a_mode2>
Table 1-2 ARM instruction set summary (continued)
ARM DDI 0165B