SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 12

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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Figure 4-12
Figure 4-13
Figure 5-1
Figure 5-2
Figure 5-3
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
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Figure 6-11
Figure 7-1
Figure 7-2
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Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
Figure 9-8
Figure 9-9
Figure C-1
Figure C-2
Figure C-3
Figure C-4
Figure C-5
Figure C-6
Figure C-7
Figure C-8
Figure C-9
Figure C-10
Figure C-11
Figure C-12
Figure C-13
Copyright © 2000 ARM Limited. All rights reserved.
Use of CLKEN ............................................................................ 4-31
Alteration of next memory request during waited bus cycle ....... 4-32
Retaking the FIQ exception .......................................................... 5-4
Stopping CLK for power saving .................................................... 5-5
Using CLK and CLKEN for best interrupt latency ......................... 5-6
ARM9E-S LDC/STC cycle timing ................................................. 6-4
ARM9E-S coprocessor clocking ................................................... 6-5
ARM9E-S MCR or MRC transfer timing ....................................... 6-8
ARM9E-S MCRR or MRRC transfer timing ................................ 6-10
ARM9E-S interlocked MCR ........................................................ 6-12
ARM9E-S interlocked MCRR ..................................................... 6-13
ARM9E-S late-canceled CDP .................................................... 6-14
ARM9E-S privileged instructions ................................................ 6-16
ARM9E-S busy waiting and interrupts ........................................ 6-17
ARM9E-S coprocessor 15 MCRs ............................................... 6-18
Coprocessor connections ........................................................... 6-19
Typical debug system ................................................................... 7-3
ARM9E-S block diagram .............................................................. 7-5
The ARM9E-S, TAP controller, and EmbeddedICE-RT ............... 7-6
Breakpoint timing .......................................................................... 7-9
Watchpoint entry with data processing instruction ..................... 7-11
Watchpoint entry with branch ..................................................... 7-12
Clock synchronization ................................................................ 7-14
Debug comms channel control register ...................................... 7-17
Coprocessor 14 monitor mode debug status register format ..... 7-18
Instruction memory interface timing ............................................. 9-2
Data memory interface timing ..................................................... 9-3
Clock enable timing ...................................................................... 9-3
Coprocessor interface timing ........................................................ 9-4
Exception and configuration timing .............................................. 9-4
Debug interface timing ................................................................. 9-5
Interrupt sensitivity status timing .................................................. 9-5
JTAG interface timing ................................................................... 9-6
DBGSDOUT to DBGTDO relationship ......................................... 9-7
ARM9E-S scan chain arrangements ............................................ C-2
Test access port controller state transitions ................................. C-4
ID code register format ............................................................... C-11
Typical scan chain cell ............................................................... C-13
Debug exit sequence .................................................................. C-22
Debug state entry ....................................................................... C-23
ARM9E-S EmbeddedICE macrocell overview ........................... C-30
Watchpoint control register for data comparison ........................ C-31
Watchpoint control register for instruction comparison .............. C-32
Debug control register format ..................................................... C-34
Debug status register ................................................................. C-35
Debug control and status register structure ............................... C-37
Vector catch register .................................................................. C-38
ARM DDI 0165B