SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 150

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7-12
WDATA[31:0]
RDATA[31:0]
DBGDEWPT
INSTR[31:0]
DBGACK
DA[31:0]
InMREQ
IA[31:1]
CLK
Although instruction 5 enters the Execute stage, it is not executed, and there is no state
update as a result of this instruction.
Once the debugging session is complete, normal continuation involves a return to
instruction 5, the next instruction in the code sequence which has not yet been executed.
The instruction following the instruction that generated the watchpoint might have
modified the Program Counter (PC). If this happens, it is not possible to determine the
instruction that caused the watchpoint. A timing diagram showing debug entry after a
watchpoint where the next instruction is a branch is shown in Figure 7-6.
You can always restart the processor. When the processor has entered debug state, the
ARM9E-S core can be interrogated to determine its state. In the case of a watchpoint,
the PC contains a value that is five instructions on from the address of the next
instruction to be executed. Therefore, if on entry to debug state, in ARM state, the
instruction
returns to the next instruction in the code sequence.
Copyright © 2000 ARM Limited. All rights reserved.
SUB PC, PC, #20
is scanned in and the processor restarted, execution flow
Figure 7-6 Watchpoint entry with branch
ARM DDI 0165B