SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 239

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.5
ARM DDI 0165B
ARM9E-S debugger considerations
There are a number of differences between the ARM9TDMI and ARM9E-S that a
JTAG debugger must be aware of:
•
•
•
•
The EmbeddedICE version number in the debug channel status register is
different. See Debug comms channel control register on page 7-17.
From (test) reset, the ARM9E-S is configured into monitor mode debug. A
debugger requiring the ARM processor halt mode debug features must clear the
monitor mode enable bit in the debug control register. See Debug control register
on page C-34.
There are a number of instructions that have different cycle counts on ARM9E-S
to ARM9TDMI. In particular, the MRS instruction always requires two cycles to
execute on ARM9E-S. See Chapter 8 Instruction Cycle Times for more details on
instruction cycle timing.
The NV condition code cannot be used to provide a convenient single-cycle
non-interlocking
ARMv5TE architecture. A special opcode,
single-cycle, non-interlocking
UNPREDICTABLE part of the instruction space, so that its behavior cannot be
guaranteed over all ARM variants.
Copyright © 2000 ARM Limited. All rights reserved.
NOP
operation. This is due to ARM9E-S implementing the
NOP
Differences Between the ARM9E-S and the ARM9TDMI
for ARM9E-S. This opcode is using an
0xE320 F000
provides a guaranteed
B-9