SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 195

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.19
ARM DDI 0165B
PLD
A
address is calculated and broadcast on DA[31:0]. DnMREQ and DSEQ indicate an
internal cycle, and DnSPEC is asserted.
Table 8-26 shows the cycle timings for PLD instructions.
Cycle
1
PLD
operation executes in a single cycle. During the Execute cycle, the prefetch
Copyright © 2000 ARM Limited. All rights reserved.
IA
pc+3i
InMREQ,
ISEQ
S cycle
INSTR
(pc+2i)
(pc+3i)
DA
da
Table 8-26 PLD operation cycle timing
DnMREQ,
DSEQ
I cycle
RDATA
-
Instruction Cycle Times
WDATA
-
8-35